20 #include "hw/qdev-properties.h"
28 /* 32-bit register indices. */
70     uint32_t din_new = s->regs[NPCM7XX_GPIO_DIN];  in npcm7xx_gpio_update_events()
72     /* Trigger on high level */  in npcm7xx_gpio_update_events()
73     s->regs[NPCM7XX_GPIO_EVST] |= din_new & ~s->regs[NPCM7XX_GPIO_EVTYP];  in npcm7xx_gpio_update_events()
74     /* Trigger on both edges */  in npcm7xx_gpio_update_events()
75     s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & s->regs[NPCM7XX_GPIO_EVTYP]  in npcm7xx_gpio_update_events()
76                                    & s->regs[NPCM7XX_GPIO_EVBE]);  in npcm7xx_gpio_update_events()
77     /* Trigger on rising edge */  in npcm7xx_gpio_update_events()
78     s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & din_new  in npcm7xx_gpio_update_events()
79                                    & s->regs[NPCM7XX_GPIO_EVTYP]);  in npcm7xx_gpio_update_events()
81     trace_npcm7xx_gpio_update_events(DEVICE(s)->canonical_path,  in npcm7xx_gpio_update_events()
82                                      s->regs[NPCM7XX_GPIO_EVST],  in npcm7xx_gpio_update_events()
83                                      s->regs[NPCM7XX_GPIO_EVEN]);  in npcm7xx_gpio_update_events()
84     qemu_set_irq(s->irq, !!(s->regs[NPCM7XX_GPIO_EVST]  in npcm7xx_gpio_update_events()
85                             & s->regs[NPCM7XX_GPIO_EVEN]));  in npcm7xx_gpio_update_events()
98     drive_lvl = s->regs[NPCM7XX_GPIO_DOUT] ^ s->regs[NPCM7XX_GPIO_POL];  in npcm7xx_gpio_update_pins()
100     drive_en = s->regs[NPCM7XX_GPIO_OE] & ~(s->regs[NPCM7XX_GPIO_OTYP]  in npcm7xx_gpio_update_pins()
106     undefined = drive_en & s->ext_driven & (drive_lvl ^ s->ext_level);  in npcm7xx_gpio_update_pins()
110                       DEVICE(s)->canonical_path, undefined);  in npcm7xx_gpio_update_pins()
113     not_driven = ~(drive_en | s->ext_driven);  in npcm7xx_gpio_update_pins()
114     pin_diff = s->pin_level;  in npcm7xx_gpio_update_pins()
117     s->pin_level = s->ext_level & s->ext_driven;  in npcm7xx_gpio_update_pins()
119     s->pin_level |= drive_lvl & drive_en;  in npcm7xx_gpio_update_pins()
120     /* Pull up undriven pins with internal pull-up enabled. */  in npcm7xx_gpio_update_pins()
121     s->pin_level |= not_driven & s->regs[NPCM7XX_GPIO_PU];  in npcm7xx_gpio_update_pins()
123     undefined |= not_driven & ~(s->regs[NPCM7XX_GPIO_PU]  in npcm7xx_gpio_update_pins()
124                                 | s->regs[NPCM7XX_GPIO_PD]);  in npcm7xx_gpio_update_pins()
127     pin_diff ^= s->pin_level;  in npcm7xx_gpio_update_pins()
135                 int level = (undefined & mask) ? -1 : !!(s->pin_level & mask);  in npcm7xx_gpio_update_pins()
136                 trace_npcm7xx_gpio_set_output(DEVICE(s)->canonical_path,  in npcm7xx_gpio_update_pins()
138                 qemu_set_irq(s->output[i], level);  in npcm7xx_gpio_update_pins()
144     din_old = s->regs[NPCM7XX_GPIO_DIN];  in npcm7xx_gpio_update_pins()
145     s->regs[NPCM7XX_GPIO_DIN] = ((s->pin_level & s->regs[NPCM7XX_GPIO_IEM])  in npcm7xx_gpio_update_pins()
146                                  ^ s->regs[NPCM7XX_GPIO_POL]);  in npcm7xx_gpio_update_pins()
149     npcm7xx_gpio_update_events(s, din_old ^ s->regs[NPCM7XX_GPIO_DIN]);  in npcm7xx_gpio_update_pins()
154     return s->regs[NPCM7XX_GPIO_TLOCK1] == 1;  in npcm7xx_gpio_is_locked()
167         value = s->regs[reg];  in npcm7xx_gpio_regs_read()
173                       "%s: read from write-only register 0x%" HWADDR_PRIx "\n",  in npcm7xx_gpio_regs_read()
174                       DEVICE(s)->canonical_path, addr);  in npcm7xx_gpio_regs_read()
177     default:  in npcm7xx_gpio_regs_read()
180                       DEVICE(s)->canonical_path, addr);  in npcm7xx_gpio_regs_read()
184     trace_npcm7xx_gpio_read(DEVICE(s)->canonical_path, addr, value);  in npcm7xx_gpio_regs_read()
197     trace_npcm7xx_gpio_write(DEVICE(s)->canonical_path, addr, v);  in npcm7xx_gpio_regs_write()
202             if (s->regs[NPCM7XX_GPIO_TLOCK2] == NPCM7XX_GPIO_LOCK_MAGIC2 &&  in npcm7xx_gpio_regs_write()
204                 s->regs[NPCM7XX_GPIO_TLOCK1] = 0;  in npcm7xx_gpio_regs_write()
205                 s->regs[NPCM7XX_GPIO_TLOCK2] = 0;  in npcm7xx_gpio_regs_write()
210             s->regs[reg] = value;  in npcm7xx_gpio_regs_write()
213         default:  in npcm7xx_gpio_regs_write()
216                           DEVICE(s)->canonical_path, addr);  in npcm7xx_gpio_regs_write()
226         s->regs[NPCM7XX_GPIO_TLOCK1] = 1;  in npcm7xx_gpio_regs_write()
227         s->regs[NPCM7XX_GPIO_TLOCK2] = 0;  in npcm7xx_gpio_regs_write()
232                       "%s: write to read-only register @ 0x%" HWADDR_PRIx "\n",  in npcm7xx_gpio_regs_write()
233                       DEVICE(s)->canonical_path, addr);  in npcm7xx_gpio_regs_write()
243         diff = s->regs[reg] ^ value;  in npcm7xx_gpio_regs_write()
244         s->regs[reg] = value;  in npcm7xx_gpio_regs_write()
249         s->regs[NPCM7XX_GPIO_DOUT] |= value;  in npcm7xx_gpio_regs_write()
253         s->regs[NPCM7XX_GPIO_DOUT] &= ~value;  in npcm7xx_gpio_regs_write()
257         s->regs[NPCM7XX_GPIO_OE] |= value;  in npcm7xx_gpio_regs_write()
261         s->regs[NPCM7XX_GPIO_OE] &= ~value;  in npcm7xx_gpio_regs_write()
268         s->regs[reg] = value;  in npcm7xx_gpio_regs_write()
273         s->regs[NPCM7XX_GPIO_EVEN] |= value;  in npcm7xx_gpio_regs_write()
277         s->regs[NPCM7XX_GPIO_EVEN] &= ~value;  in npcm7xx_gpio_regs_write()
282         s->regs[reg] &= ~value;  in npcm7xx_gpio_regs_write()
291         s->regs[reg] = value;  in npcm7xx_gpio_regs_write()
298         s->regs[reg] = value;  in npcm7xx_gpio_regs_write()
305         qemu_log_mask(LOG_UNIMP, "%s: Per-pin lock is not implemented\n",  in npcm7xx_gpio_regs_write()
309     default:  in npcm7xx_gpio_regs_write()
312                       DEVICE(s)->canonical_path, addr);  in npcm7xx_gpio_regs_write()
332     trace_npcm7xx_gpio_set_input(DEVICE(s)->canonical_path, line, level);  in npcm7xx_gpio_set_input()
336     s->ext_driven = deposit32(s->ext_driven, line, 1, level >= 0);  in npcm7xx_gpio_set_input()
337     s->ext_level = deposit32(s->ext_level, line, 1, level > 0);  in npcm7xx_gpio_set_input()
346     memset(s->regs, 0, sizeof(s->regs));  in npcm7xx_gpio_enter_reset()
348     s->regs[NPCM7XX_GPIO_PU] = s->reset_pu;  in npcm7xx_gpio_enter_reset()
349     s->regs[NPCM7XX_GPIO_PD] = s->reset_pd;  in npcm7xx_gpio_enter_reset()
350     s->regs[NPCM7XX_GPIO_OSRC] = s->reset_osrc;  in npcm7xx_gpio_enter_reset()
351     s->regs[NPCM7XX_GPIO_ODSC] = s->reset_odsc;  in npcm7xx_gpio_enter_reset()
358     npcm7xx_gpio_update_pins(s, -1);  in npcm7xx_gpio_hold_reset()
366     memory_region_init_io(&s->mmio, obj, &npcm7xx_gpio_regs_ops, s,  in npcm7xx_gpio_init()
368     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);  in npcm7xx_gpio_init()
369     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);  in npcm7xx_gpio_init()
372     qdev_init_gpio_out(dev, s->output, NPCM7XX_GPIO_NR_PINS);  in npcm7xx_gpio_init()
376     .name = "npcm7xx-gpio",
389     /* Bit n set => pin n has pullup enabled by default. */
390     DEFINE_PROP_UINT32("reset-pullup", NPCM7xxGPIOState, reset_pu, 0),
391     /* Bit n set => pin n has pulldown enabled by default. */
392     DEFINE_PROP_UINT32("reset-pulldown", NPCM7xxGPIOState, reset_pd, 0),
393     /* Bit n set => pin n has high slew rate by default. */
394     DEFINE_PROP_UINT32("reset-osrc", NPCM7xxGPIOState, reset_osrc, 0),
395     /* Bit n set => pin n has high drive strength by default. */
396     DEFINE_PROP_UINT32("reset-odsc", NPCM7xxGPIOState, reset_odsc, 0),
406     dc->desc = "NPCM7xx GPIO Controller";  in npcm7xx_gpio_class_init()
407     dc->vmsd = &vmstate_npcm7xx_gpio;  in npcm7xx_gpio_class_init()
408     reset->phases.enter = npcm7xx_gpio_enter_reset;  in npcm7xx_gpio_class_init()
409     reset->phases.hold = npcm7xx_gpio_hold_reset;  in npcm7xx_gpio_class_init()