Lines Matching +full:default +full:- +full:trigger
4 * Copyright (c) 2019-2024, IBM Corporation..
6 * SPDX-License-Identifier: GPL-2.0-or-later
16 #include "hw/qdev-properties.h"
26 return xrc->get_config(xrtr); in xive2_router_get_config()
33 return xrc->get_block_id(xrtr); in xive2_router_get_block_id()
40 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 | in xive2_nvp_reporting_addr()
41 xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7); in xive2_nvp_reporting_addr()
56 * The per-priority backlog counters are 24-bit and the structure in xive2_nvgc_get_backlog()
57 * is stored in big endian. NVGC is 32-bytes long, so 24-bytes from in xive2_nvgc_get_backlog()
58 * w2, which fits 8 priorities * 24-bits per priority. in xive2_nvgc_get_backlog()
60 ptr = (uint8_t *)&nvgc->w2 + priority * 3; in xive2_nvgc_get_backlog()
81 * The per-priority backlog counters are 24-bit and the structure in xive2_nvgc_set_backlog()
84 ptr = (uint8_t *)&nvgc->w2 + priority * 3; in xive2_nvgc_set_backlog()
86 shift = 8 * (2 - i); in xive2_nvgc_set_backlog()
105 return -1; in xive2_presenter_nvgc_backlog_op()
109 return -1; in xive2_presenter_nvgc_backlog_op()
118 * 0b1- => read in xive2_presenter_nvgc_backlog_op()
125 count -= val; in xive2_presenter_nvgc_backlog_op()
149 return -1; in xive2_presenter_nvp_backlog_op()
153 return -1; in xive2_presenter_nvp_backlog_op()
162 * 0b1- => read in xive2_presenter_nvp_backlog_op()
186 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), in xive2_eas_pic_print_info()
187 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), in xive2_eas_pic_print_info()
188 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); in xive2_eas_pic_print_info()
194 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); in xive2_end_queue_pic_print_info()
195 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); in xive2_end_queue_pic_print_info()
200 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window in xive2_end_queue_pic_print_info()
203 qindex = (qindex - (width - 1)) & (qentries - 1); in xive2_end_queue_pic_print_info()
206 uint32_t qdata = -1; in xive2_end_queue_pic_print_info()
214 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", in xive2_end_queue_pic_print_info()
216 qindex = (qindex + 1) & (qentries - 1); in xive2_end_queue_pic_print_info()
224 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); in xive2_end_pic_print_info()
225 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); in xive2_end_pic_print_info()
226 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); in xive2_end_pic_print_info()
229 uint32_t nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); in xive2_end_pic_print_info()
230 uint32_t nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); in xive2_end_pic_print_info()
231 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); in xive2_end_pic_print_info()
238 pq = xive_get_field32(END2_W1_ESn, end->w1); in xive2_end_pic_print_info()
244 pq & XIVE_ESB_VAL_P ? 'P' : '-', in xive2_end_pic_print_info()
245 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', in xive2_end_pic_print_info()
246 xive2_end_is_valid(end) ? 'v' : '-', in xive2_end_pic_print_info()
247 xive2_end_is_enqueue(end) ? 'q' : '-', in xive2_end_pic_print_info()
248 xive2_end_is_notify(end) ? 'n' : '-', in xive2_end_pic_print_info()
249 xive2_end_is_backlog(end) ? 'b' : '-', in xive2_end_pic_print_info()
250 xive2_end_is_precluded_escalation(end) ? 'p' : '-', in xive2_end_pic_print_info()
251 xive2_end_is_escalate(end) ? 'e' : '-', in xive2_end_pic_print_info()
252 xive2_end_is_escalate_end(end) ? 'N' : '-', in xive2_end_pic_print_info()
253 xive2_end_is_uncond_escalation(end) ? 'u' : '-', in xive2_end_pic_print_info()
254 xive2_end_is_silent_escalation(end) ? 's' : '-', in xive2_end_pic_print_info()
255 xive2_end_is_firmware1(end) ? 'f' : '-', in xive2_end_pic_print_info()
256 xive2_end_is_firmware2(end) ? 'F' : '-', in xive2_end_pic_print_info()
257 xive2_end_is_ignore(end) ? 'i' : '-', in xive2_end_pic_print_info()
258 xive2_end_is_crowd(end) ? 'c' : '-', in xive2_end_pic_print_info()
272 Xive2Eas *eas = (Xive2Eas *) &end->w4; in xive2_end_eas_pic_print_info()
279 pq = xive_get_field32(END2_W1_ESe, end->w1); in xive2_end_eas_pic_print_info()
283 pq & XIVE_ESB_VAL_P ? 'P' : '-', in xive2_end_eas_pic_print_info()
284 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', in xive2_end_eas_pic_print_info()
287 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), in xive2_end_eas_pic_print_info()
288 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), in xive2_end_eas_pic_print_info()
289 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); in xive2_end_eas_pic_print_info()
294 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); in xive2_nvp_pic_print_info()
295 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); in xive2_nvp_pic_print_info()
304 xive_get_field32(NVP2_W2_IPB, nvp->w2), in xive2_nvp_pic_print_info()
305 xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0)); in xive2_nvp_pic_print_info()
315 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); in xive2_nvp_pic_print_info()
318 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); in xive2_nvp_pic_print_info()
333 xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0)); in xive2_nvgc_pic_print_info()
344 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); in xive2_end_enqueue()
345 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); in xive2_end_enqueue()
346 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); in xive2_end_enqueue()
359 qindex = (qindex + 1) & (qentries - 1); in xive2_end_enqueue()
362 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); in xive2_end_enqueue()
365 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); in xive2_end_enqueue()
367 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); in xive2_end_enqueue()
380 * The 6-bit group level is split into a 2-bit crowd and 4-bit in xive2_pgofnext()
389 mask = (1 << next_blk) - 1; in xive2_pgofnext()
394 mask = (1 << next_idx) - 1; in xive2_pgofnext()
474 xive2_nvgc_set_backlog(&nvgc, group_prio, count - 1); in xive2_presenter_backlog_decr()
480 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode
484 * - if a context is enabled with the H bit set, the VP context
489 * - the H bit cannot be changed while the V bit is set, i.e. a
498 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; in xive2_tctx_save_ctx()
499 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_save_ctx()
501 uint8_t *regs = &tctx->regs[ring]; in xive2_tctx_save_ctx()
577 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; in xive2_tctx_hw_cam_line()
578 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_hw_cam_line()
582 uint8_t tid_mask = (1 << tid_shift) - 1; in xive2_tctx_hw_cam_line()
591 uint32_t target_ringw2 = xive_tctx_word2(&tctx->regs[ring]); in xive2_tm_pull_ctx()
609 uint32_t ringw2 = xive_tctx_word2(&tctx->regs[cur_ring]); in xive2_tm_pull_ctx()
611 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); in xive2_tm_pull_ctx()
640 uint8_t *regs = tctx->regs; in xive2_tm_report_line_gen1()
646 * hand-picked information to fit in 16 bytes. in xive2_tm_report_line_gen1()
717 &tctx->regs, sizeof(tctx->regs), in xive2_tm_pull_ctx_ol()
748 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; in xive2_tctx_restore_os_ctx()
749 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_restore_os_ctx()
758 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2); in xive2_tctx_restore_os_ctx()
759 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); in xive2_tctx_restore_os_ctx()
762 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; in xive2_tctx_restore_os_ctx()
763 tctx->regs[TM_QW1_OS + TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2); in xive2_tctx_restore_os_ctx()
764 tctx->regs[TM_QW1_OS + TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2); in xive2_tctx_restore_os_ctx()
765 tctx->regs[TM_QW1_OS + TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2); in xive2_tctx_restore_os_ctx()
767 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1); in xive2_tctx_restore_os_ctx()
768 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); in xive2_tctx_restore_os_ctx()
769 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); in xive2_tctx_restore_os_ctx()
776 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); in xive2_tctx_restore_os_ctx()
795 uint8_t *regs = &tctx->regs[TM_QW1_OS]; in xive2_tctx_need_resend()
851 * Updating the OS CAM line can trigger a resend of interrupt
869 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive2_tm_push_os_ctx()
874 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8); in xive2_tm_push_os_ctx()
876 default: in xive2_tm_push_os_ctx()
894 w2 = xive_tctx_word2(&tctx->regs[ring]); in xive2_tctx_get_nvp_indexes()
898 return -1; in xive2_tctx_get_nvp_indexes()
904 return -1; in xive2_tctx_get_nvp_indexes()
910 return -1; in xive2_tctx_get_nvp_indexes()
912 cam = xive2_tctx_hw_cam_line(tctx->xptr, tctx); in xive2_tctx_get_nvp_indexes()
914 default: in xive2_tctx_get_nvp_indexes()
915 return -1; in xive2_tctx_get_nvp_indexes()
924 uint8_t *regs = &tctx->regs[ring]; in xive2_tctx_set_cppr()
925 Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr); in xive2_tctx_set_cppr()
933 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, in xive2_tctx_set_cppr()
955 uint8_t *pregs = &tctx->regs[TM_QW2_HV_POOL]; in xive2_tctx_set_cppr()
996 * interrupt needs to be re-added to the backlog and in xive2_tctx_set_cppr()
997 * re-triggered (see re-trigger END info in the NVGC in xive2_tctx_set_cppr()
1029 backlog_prio = xive2_presenter_backlog_scan(tctx->xptr, in xive2_tctx_set_cppr()
1032 tctx->regs[ring_min + TM_LSMFB] = backlog_prio; in xive2_tctx_set_cppr()
1034 xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx, in xive2_tctx_set_cppr()
1057 uint8_t *regs = &tctx->regs[ring]; in xive2_tctx_set_target()
1077 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); in xive2_router_get_eas()
1086 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); in xive2_router_get_pq()
1095 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); in xive2_router_set_pq()
1103 return xrc->get_end(xrtr, end_blk, end_idx, end); in xive2_router_get_end()
1111 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); in xive2_router_write_end()
1119 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); in xive2_router_get_nvp()
1127 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); in xive2_router_write_nvp()
1136 return xrc->get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); in xive2_router_get_nvgc()
1145 return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); in xive2_router_write_nvgc()
1167 block_mask &= ~(size - 1); in xive2_get_vp_block_mask()
1184 index_mask &= ~(size - 1); in xive2_get_vp_index_mask()
1190 * The thread context register words are in big-endian format.
1199 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); in xive2_presenter_tctx_match()
1200 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); in xive2_presenter_tctx_match()
1201 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); in xive2_presenter_tctx_match()
1202 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); in xive2_presenter_tctx_match()
1210 * i=1: VP-group notification (bits ignored at the end of the in xive2_presenter_tctx_match()
1217 /* For VP-group notifications, threads with LGS=0 are excluded */ in xive2_presenter_tctx_match()
1221 !(cam_ignore && tctx->regs[TM_QW3_HV_PHYS + TM_LGS] == 0) && in xive2_presenter_tctx_match()
1230 !(cam_ignore && tctx->regs[TM_QW2_HV_POOL + TM_LGS] == 0) && in xive2_presenter_tctx_match()
1239 !(cam_ignore && tctx->regs[TM_QW1_OS + TM_LGS] == 0) && in xive2_presenter_tctx_match()
1246 /* F=1 : User level Event-Based Branch (EBB) notification */ in xive2_presenter_tctx_match()
1257 return -1; in xive2_presenter_tctx_match()
1264 uint8_t *alt_regs = &tctx->regs[alt_ring]; in xive2_tm_irq_precluded()
1268 * but for VP-group notification, we still need to look at the in xive2_tm_irq_precluded()
1280 uint8_t *regs = &tctx->regs[ring]; in xive2_tm_set_lsmfb()
1283 * Called by the router during a VP-group notification when the in xive2_tm_set_lsmfb()
1295 assert(xrtr->xfb); in xive2_router_realize()
1307 uint8_t pq = xive_get_field32(end_esmask, end->w1); in xive2_router_end_es_notify()
1310 if (pq != xive_get_field32(end_esmask, end->w1)) { in xive2_router_end_es_notify()
1311 end->w1 = xive_set_field32(end_esmask, end->w1, pq); in xive2_router_end_es_notify()
1320 * An END trigger can come from an event trigger (IPI or HW) or from
1321 * another chip. We don't model the PowerBus but the END trigger
1371 * F=1 : User level Event-Based Branch (EBB) notification, no in xive2_router_end_notify()
1400 found = xive_presenter_notify(xrtr->xfb, format, nvx_blk, nvx_idx, in xive2_router_end_notify()
1414 * - specific VP: update the NVP structure if backlog is activated in xive2_router_end_notify()
1415 * - VP-group: update the backlog counter for that priority in the NVG in xive2_router_end_notify()
1460 * For groups and crowds, the per-priority backlog in xive2_router_end_notify()
1487 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xrtr->xfb); in xive2_router_end_notify()
1488 xfc->broadcast(xrtr->xfb, nvx_blk, nvx_idx, in xive2_router_end_notify()
1507 * the EAS in w4-5 in xive2_router_end_notify()
1526 * The END trigger becomes an Escalation trigger in xive2_router_end_notify()
1580 * The event trigger becomes an END trigger in xive2_router_notify()
1589 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb,
1598 dc->desc = "XIVE2 Router Engine"; in xive2_router_class_init()
1601 dc->realize = xive2_router_realize; in xive2_router_class_init()
1602 xnc->notify = xive2_router_notify; in xive2_router_class_init()
1639 end_blk = xive2_router_get_block_id(xsrc->xrtr); in xive2_end_source_read()
1640 end_idx = addr >> (xsrc->esb_shift + 1); in xive2_end_source_read()
1642 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { in xive2_end_source_read()
1645 return -1; in xive2_end_source_read()
1651 return -1; in xive2_end_source_read()
1654 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : in xive2_end_source_read()
1675 default: in xive2_end_source_read()
1678 return -1; in xive2_end_source_read()
1683 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); in xive2_end_source_read()
1705 end_blk = xive2_router_get_block_id(xsrc->xrtr); in xive2_end_source_write()
1706 end_idx = addr >> (xsrc->esb_shift + 1); in xive2_end_source_write()
1708 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { in xive2_end_source_write()
1720 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : in xive2_end_source_write()
1744 default: in xive2_end_source_write()
1752 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); in xive2_end_source_write()
1779 assert(xsrc->xrtr); in xive2_end_source_realize()
1781 if (!xsrc->nr_ends) { in xive2_end_source_realize()
1786 if (xsrc->esb_shift != XIVE_ESB_4K && in xive2_end_source_realize()
1787 xsrc->esb_shift != XIVE_ESB_64K) { in xive2_end_source_realize()
1796 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), in xive2_end_source_realize()
1798 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); in xive2_end_source_realize()
1802 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0),
1812 dc->desc = "XIVE END Source"; in xive2_end_source_class_init()
1814 dc->realize = xive2_end_source_realize; in xive2_end_source_class_init()
1815 dc->user_creatable = false; in xive2_end_source_class_init()