Lines Matching +full:default +full:- +full:trigger
4 * Copyright (c) 2018-2020, IBM Corporation.
7 * COPYING file in the top-level directory.
14 #include "hw/pci-host/pnv_phb4_regs.h"
15 #include "hw/pci-host/pnv_phb4.h"
21 #include "hw/qdev-properties.h"
27 (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__)
31 (pec)->chip_id, (pec)->index, ## __VA_ARGS__)
35 PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); in pnv_phb4_find_cfg_dev()
36 uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; in pnv_phb4_find_cfg_dev()
49 return pci_find_device(pci->bus, bus, devfn); in pnv_phb4_find_cfg_dev()
66 cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; in pnv_phb4_config_write()
71 * conventional pci device can be behind pcie-to-pci bridge. in pnv_phb4_config_write()
85 default: in pnv_phb4_config_write()
102 cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; in pnv_phb4_config_read()
107 * conventional pci device can be behind pcie-to-pci bridge. in pnv_phb4_config_read()
120 default: in pnv_phb4_config_read()
131 PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); in pnv_phb4_rc_config_write()
139 pdev = pci_find_device(pci->bus, 0, 0); in pnv_phb4_rc_config_write()
152 PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); in pnv_phb4_rc_config_read()
161 pdev = pci_find_device(pci->bus, 0, 0); in pnv_phb4_rc_config_read()
178 if (memory_region_is_mapped(&phb->mr_mmio[index])) { in pnv_phb4_check_mbt()
180 memory_region_del_subregion(phb->mr_mmio[index].container, in pnv_phb4_check_mbt()
181 &phb->mr_mmio[index]); in pnv_phb4_check_mbt()
185 mbe0 = phb->ioda_MBT[(index << 1)]; in pnv_phb4_check_mbt()
186 mbe1 = phb->ioda_MBT[(index << 1) + 1]; in pnv_phb4_check_mbt()
200 start = phb->regs[PHB_M32_START_ADDR >> 3]; in pnv_phb4_check_mbt()
203 size = 0x100000000 - start; in pnv_phb4_check_mbt()
206 start = base | (phb->regs[PHB_M64_UPPER_BITS >> 3]); in pnv_phb4_check_mbt()
212 if (memory_region_is_mapped(&phb->mmbar0) && in pnv_phb4_check_mbt()
213 base >= phb->mmio0_base && in pnv_phb4_check_mbt()
214 (base + size) <= (phb->mmio0_base + phb->mmio0_size)) { in pnv_phb4_check_mbt()
215 parent = &phb->mmbar0; in pnv_phb4_check_mbt()
216 base -= phb->mmio0_base; in pnv_phb4_check_mbt()
217 } else if (memory_region_is_mapped(&phb->mmbar1) && in pnv_phb4_check_mbt()
218 base >= phb->mmio1_base && in pnv_phb4_check_mbt()
219 (base + size) <= (phb->mmio1_base + phb->mmio1_size)) { in pnv_phb4_check_mbt()
220 parent = &phb->mmbar1; in pnv_phb4_check_mbt()
221 base -= phb->mmio1_base; in pnv_phb4_check_mbt()
228 snprintf(name, sizeof(name), "phb4-mbar%d", index); in pnv_phb4_check_mbt()
229 memory_region_init_alias(&phb->mr_mmio[index], OBJECT(phb), name, in pnv_phb4_check_mbt()
230 &phb->pci_mmio, start, size); in pnv_phb4_check_mbt()
231 memory_region_add_subregion(parent, base, &phb->mr_mmio[index]); in pnv_phb4_check_mbt()
237 uint32_t num_windows = phb->big_phb ? PNV_PHB4_MAX_MMIO_WINDOWS : in pnv_phb4_check_all_mbt()
248 uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3]; in pnv_phb4_ioda_access()
256 tptr = phb->ioda_LIST; in pnv_phb4_ioda_access()
260 tptr = phb->ioda_MIST; in pnv_phb4_ioda_access()
261 mask = phb->big_phb ? PNV_PHB4_MAX_MIST : (PNV_PHB4_MAX_MIST >> 1); in pnv_phb4_ioda_access()
262 mask -= 1; in pnv_phb4_ioda_access()
265 mask = phb->big_phb ? 127 : 63; in pnv_phb4_ioda_access()
268 mask = phb->big_phb ? 15 : 7; in pnv_phb4_ioda_access()
272 mask = phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1); in pnv_phb4_ioda_access()
273 mask -= 1; in pnv_phb4_ioda_access()
276 tptr = phb->ioda_TVT; in pnv_phb4_ioda_access()
277 mask = phb->big_phb ? PNV_PHB4_MAX_TVEs : (PNV_PHB4_MAX_TVEs >> 1); in pnv_phb4_ioda_access()
278 mask -= 1; in pnv_phb4_ioda_access()
282 mask = phb->big_phb ? 1023 : 511; in pnv_phb4_ioda_access()
285 tptr = phb->ioda_MBT; in pnv_phb4_ioda_access()
286 mask = phb->big_phb ? PNV_PHB4_MAX_MBEs : (PNV_PHB4_MAX_MBEs >> 1); in pnv_phb4_ioda_access()
287 mask -= 1; in pnv_phb4_ioda_access()
290 tptr = phb->ioda_MDT; in pnv_phb4_ioda_access()
291 mask = phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1); in pnv_phb4_ioda_access()
292 mask -= 1; in pnv_phb4_ioda_access()
295 tptr = phb->ioda_PEEV; in pnv_phb4_ioda_access()
296 mask = phb->big_phb ? PNV_PHB4_MAX_PEEVs : (PNV_PHB4_MAX_PEEVs >> 1); in pnv_phb4_ioda_access()
297 mask -= 1; in pnv_phb4_ioda_access()
299 default: in pnv_phb4_ioda_access()
318 phb->regs[PHB_IODA_ADDR >> 3] = adreg; in pnv_phb4_ioda_access()
331 return ((uint64_t)(phb->ioda_PEST_AB[idx] & 1)) << 63; in pnv_phb4_ioda_read()
333 return ((uint64_t)(phb->ioda_PEST_AB[idx] & 2)) << 62; in pnv_phb4_ioda_read()
350 phb->ioda_PEST_AB[idx] &= ~1; in pnv_phb4_ioda_write()
351 phb->ioda_PEST_AB[idx] |= (val >> 63) & 1; in pnv_phb4_ioda_write()
353 phb->ioda_PEST_AB[idx] &= ~2; in pnv_phb4_ioda_write()
354 phb->ioda_PEST_AB[idx] |= (val >> 62) & 2; in pnv_phb4_ioda_write()
365 uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3]; in pnv_phb4_ioda_write()
394 phb->ioda_MBT[idx ^ 1] &= 0x7fffffffffffffffull; in pnv_phb4_ioda_write()
395 phb->ioda_MBT[idx ^ 1] |= 0x8000000000000000ull & val; in pnv_phb4_ioda_write()
400 default: in pnv_phb4_ioda_write()
410 QLIST_FOREACH(ds, &phb->dma_spaces, list) { in pnv_phb4_rtc_invalidate()
411 ds->pe_num = PHB_INVALID_PE; in pnv_phb4_rtc_invalidate()
417 uint64_t cfg = ds->phb->regs[PHB_PHB4_CONFIG >> 3]; in pnv_phb4_update_msi_regions()
420 if (!memory_region_is_mapped(MEMORY_REGION(&ds->msi32_mr))) { in pnv_phb4_update_msi_regions()
421 memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr), in pnv_phb4_update_msi_regions()
422 0xffff0000, &ds->msi32_mr); in pnv_phb4_update_msi_regions()
425 if (memory_region_is_mapped(MEMORY_REGION(&ds->msi32_mr))) { in pnv_phb4_update_msi_regions()
426 memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr), in pnv_phb4_update_msi_regions()
427 &ds->msi32_mr); in pnv_phb4_update_msi_regions()
432 if (!memory_region_is_mapped(MEMORY_REGION(&ds->msi64_mr))) { in pnv_phb4_update_msi_regions()
433 memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr), in pnv_phb4_update_msi_regions()
434 (1ull << 60), &ds->msi64_mr); in pnv_phb4_update_msi_regions()
437 if (memory_region_is_mapped(MEMORY_REGION(&ds->msi64_mr))) { in pnv_phb4_update_msi_regions()
438 memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr), in pnv_phb4_update_msi_regions()
439 &ds->msi64_mr); in pnv_phb4_update_msi_regions()
448 QLIST_FOREACH(ds, &phb->dma_spaces, list) { in pnv_phb4_update_all_msi_regions()
456 XiveSource *xsrc = &phb->xsrc; in pnv_phb4_update_xsrc()
459 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PGSZ_64K) { in pnv_phb4_update_xsrc()
464 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_STORE_EOI) { in pnv_phb4_update_xsrc()
475 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PQ_DISABLE) { in pnv_phb4_update_xsrc()
479 phb->xsrc.esb_shift = shift; in pnv_phb4_update_xsrc()
480 phb->xsrc.esb_flags = flags; in pnv_phb4_update_xsrc()
482 lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]); in pnv_phb4_update_xsrc()
491 bitmap_zero(xsrc->lsi_map, xsrc->nr_irqs); in pnv_phb4_update_xsrc()
493 for (i = 0; i < xsrc->nr_irqs; i++) { in pnv_phb4_update_xsrc()
519 /* Other registers are 64-bit only */ in pnv_phb4_reg_write()
552 phb->regs[PHB_LEM_FIR_ACCUM >> 3] &= val; in pnv_phb4_reg_write()
555 phb->regs[PHB_LEM_FIR_ACCUM >> 3] |= val; in pnv_phb4_reg_write()
558 phb->regs[PHB_LEM_ERROR_MASK >> 3] &= val; in pnv_phb4_reg_write()
561 phb->regs[PHB_LEM_ERROR_MASK >> 3] |= val; in pnv_phb4_reg_write()
579 changed = phb->regs[off >> 3] != val; in pnv_phb4_reg_write()
582 phb->regs[off >> 3] = val; in pnv_phb4_reg_write()
634 default: in pnv_phb4_reg_write()
654 /* Other registers are 64-bit only */ in pnv_phb4_reg_read()
661 /* Default read from cache */ in pnv_phb4_reg_read()
662 val = phb->regs[off >> 3]; in pnv_phb4_reg_read()
666 return PNV_PHB4_PEC_GET_CLASS(phb->pec)->version; in pnv_phb4_reg_read()
668 /* Read-only */ in pnv_phb4_reg_read()
672 return phb->big_phb ? 0x4008440000000400ull : 0x2008440000000200ull; in pnv_phb4_reg_read()
674 return phb->big_phb ? 0x0800000000001000ull : 0x0800000000000800ull; in pnv_phb4_reg_read()
676 return phb->big_phb ? 0x2000000000000000ull : 0x1000000000000000ull; in pnv_phb4_reg_read()
719 default: in pnv_phb4_reg_read()
745 return phb->scom_hv_ind_addr_reg; in pnv_phb4_xscom_read()
748 if (!(phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_VALID)) { in pnv_phb4_xscom_read()
752 size = (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_4B) ? 4 : 8; in pnv_phb4_xscom_read()
753 offset = GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, phb->scom_hv_ind_addr_reg); in pnv_phb4_xscom_read()
755 if (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_AUTOINC) { in pnv_phb4_xscom_read()
758 phb->scom_hv_ind_addr_reg = SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, in pnv_phb4_xscom_read()
759 phb->scom_hv_ind_addr_reg, in pnv_phb4_xscom_read()
772 offset = ((reg - PHB_SCOM_ETU_LEM_FIR) << 3) + PHB_LEM_FIR_ACCUM; in pnv_phb4_xscom_read()
779 offset = ((reg - PHB_SCOM_ETU_PMON_CONFIG) << 3) + PHB_PERFMON_CONFIG; in pnv_phb4_xscom_read()
782 default: in pnv_phb4_xscom_read()
797 phb->scom_hv_ind_addr_reg = val & 0xe000000000001fff; in pnv_phb4_xscom_write()
800 if (!(phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_VALID)) { in pnv_phb4_xscom_write()
804 size = (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_4B) ? 4 : 8; in pnv_phb4_xscom_write()
805 offset = GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, phb->scom_hv_ind_addr_reg); in pnv_phb4_xscom_write()
807 if (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_AUTOINC) { in pnv_phb4_xscom_write()
810 phb->scom_hv_ind_addr_reg = SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, in pnv_phb4_xscom_write()
811 phb->scom_hv_ind_addr_reg, in pnv_phb4_xscom_write()
824 offset = ((reg - PHB_SCOM_ETU_LEM_FIR) << 3) + PHB_LEM_FIR_ACCUM; in pnv_phb4_xscom_write()
832 offset = ((reg - PHB_SCOM_ETU_PMON_CONFIG) << 3) + PHB_PERFMON_CONFIG; in pnv_phb4_xscom_write()
835 default: in pnv_phb4_xscom_write()
857 /* All registers are read-able */ in pnv_pec_stk_nest_xscom_read()
858 return phb->nest_regs[reg]; in pnv_pec_stk_nest_xscom_read()
866 * E.g. a phb with phb_id = 4 and pec->index = 1 (PEC1) will
871 PnvPhb4PecState *pec = phb->pec; in pnv_phb4_get_phb_stack_no()
873 int index = pec->index; in pnv_phb4_get_phb_stack_no()
874 int stack_no = phb->phb_id; in pnv_phb4_get_phb_stack_no()
876 while (index--) { in pnv_phb4_get_phb_stack_no()
877 stack_no -= pecc->num_phbs[index]; in pnv_phb4_get_phb_stack_no()
886 if (memory_region_is_mapped(&phb->mr_regs)) { in pnv_phb4_update_regions()
887 memory_region_del_subregion(&phb->phbbar, &phb->mr_regs); in pnv_phb4_update_regions()
889 if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) { in pnv_phb4_update_regions()
890 memory_region_del_subregion(&phb->intbar, &phb->xsrc.esb_mmio); in pnv_phb4_update_regions()
894 if (memory_region_is_mapped(&phb->phbbar)) { in pnv_phb4_update_regions()
895 memory_region_add_subregion(&phb->phbbar, 0, &phb->mr_regs); in pnv_phb4_update_regions()
899 if (memory_region_is_mapped(&phb->intbar)) { in pnv_phb4_update_regions()
900 memory_region_add_subregion(&phb->intbar, 0, &phb->xsrc.esb_mmio); in pnv_phb4_update_regions()
909 PnvPhb4PecState *pec = phb->pec; in pnv_pec_phb_update_map()
911 uint64_t bar_en = phb->nest_regs[PEC_NEST_STK_BAR_EN]; in pnv_pec_phb_update_map()
925 if (memory_region_is_mapped(&phb->mmbar0) && in pnv_pec_phb_update_map()
927 memory_region_del_subregion(sysmem, &phb->mmbar0); in pnv_pec_phb_update_map()
929 if (memory_region_is_mapped(&phb->mmbar1) && in pnv_pec_phb_update_map()
931 memory_region_del_subregion(sysmem, &phb->mmbar1); in pnv_pec_phb_update_map()
933 if (memory_region_is_mapped(&phb->phbbar) && in pnv_pec_phb_update_map()
935 memory_region_del_subregion(sysmem, &phb->phbbar); in pnv_pec_phb_update_map()
937 if (memory_region_is_mapped(&phb->intbar) && in pnv_pec_phb_update_map()
939 memory_region_del_subregion(sysmem, &phb->intbar); in pnv_pec_phb_update_map()
946 if (!memory_region_is_mapped(&phb->mmbar0) && in pnv_pec_phb_update_map()
948 bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8; in pnv_pec_phb_update_map()
949 mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK]; in pnv_pec_phb_update_map()
951 snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-mmio0", in pnv_pec_phb_update_map()
952 pec->chip_id, pec->index, stack_no); in pnv_pec_phb_update_map()
953 memory_region_init(&phb->mmbar0, OBJECT(phb), name, size); in pnv_pec_phb_update_map()
954 memory_region_add_subregion(sysmem, bar, &phb->mmbar0); in pnv_pec_phb_update_map()
955 phb->mmio0_base = bar; in pnv_pec_phb_update_map()
956 phb->mmio0_size = size; in pnv_pec_phb_update_map()
958 if (!memory_region_is_mapped(&phb->mmbar1) && in pnv_pec_phb_update_map()
960 bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8; in pnv_pec_phb_update_map()
961 mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK]; in pnv_pec_phb_update_map()
963 snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-mmio1", in pnv_pec_phb_update_map()
964 pec->chip_id, pec->index, stack_no); in pnv_pec_phb_update_map()
965 memory_region_init(&phb->mmbar1, OBJECT(phb), name, size); in pnv_pec_phb_update_map()
966 memory_region_add_subregion(sysmem, bar, &phb->mmbar1); in pnv_pec_phb_update_map()
967 phb->mmio1_base = bar; in pnv_pec_phb_update_map()
968 phb->mmio1_size = size; in pnv_pec_phb_update_map()
970 if (!memory_region_is_mapped(&phb->phbbar) && in pnv_pec_phb_update_map()
972 bar = phb->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8; in pnv_pec_phb_update_map()
974 snprintf(name, sizeof(name), "pec-%d.%d-phb-%d", in pnv_pec_phb_update_map()
975 pec->chip_id, pec->index, stack_no); in pnv_pec_phb_update_map()
976 memory_region_init(&phb->phbbar, OBJECT(phb), name, size); in pnv_pec_phb_update_map()
977 memory_region_add_subregion(sysmem, bar, &phb->phbbar); in pnv_pec_phb_update_map()
979 if (!memory_region_is_mapped(&phb->intbar) && in pnv_pec_phb_update_map()
981 bar = phb->nest_regs[PEC_NEST_STK_INT_BAR] >> 8; in pnv_pec_phb_update_map()
983 snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-int", in pnv_pec_phb_update_map()
984 phb->pec->chip_id, phb->pec->index, stack_no); in pnv_pec_phb_update_map()
985 memory_region_init(&phb->intbar, OBJECT(phb), name, size); in pnv_pec_phb_update_map()
986 memory_region_add_subregion(sysmem, bar, &phb->intbar); in pnv_pec_phb_update_map()
997 PnvPhb4PecState *pec = phb->pec; in pnv_pec_stk_nest_xscom_write()
1002 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val & PPC_BITMASK(0, 27); in pnv_pec_stk_nest_xscom_write()
1005 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val; in pnv_pec_stk_nest_xscom_write()
1008 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val; in pnv_pec_stk_nest_xscom_write()
1011 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val & in pnv_pec_stk_nest_xscom_write()
1015 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val; in pnv_pec_stk_nest_xscom_write()
1018 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val; in pnv_pec_stk_nest_xscom_write()
1022 phb->nest_regs[reg] = val & PPC_BITMASK(0, 27); in pnv_pec_stk_nest_xscom_write()
1025 phb->nest_regs[reg] = 0; in pnv_pec_stk_nest_xscom_write()
1033 phb->nest_regs[reg] = val & PPC_BITMASK(0, 7); in pnv_pec_stk_nest_xscom_write()
1039 if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & in pnv_pec_stk_nest_xscom_write()
1044 phb->nest_regs[reg] = val & PPC_BITMASK(0, 39); in pnv_pec_stk_nest_xscom_write()
1047 if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) { in pnv_pec_stk_nest_xscom_write()
1050 phb->nest_regs[reg] = val & PPC_BITMASK(0, 41); in pnv_pec_stk_nest_xscom_write()
1053 if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) { in pnv_pec_stk_nest_xscom_write()
1056 phb->nest_regs[reg] = val & PPC_BITMASK(0, 27); in pnv_pec_stk_nest_xscom_write()
1059 phb->nest_regs[reg] = val & PPC_BITMASK(0, 3); in pnv_pec_stk_nest_xscom_write()
1064 phb->nest_regs[reg] = val & PPC_BITMASK(0, 27); in pnv_pec_stk_nest_xscom_write()
1067 phb->nest_regs[reg] = val & PPC_BITMASK(3, 5); in pnv_pec_stk_nest_xscom_write()
1070 phb->nest_regs[reg] = val & PPC_BITMASK(0, 7); in pnv_pec_stk_nest_xscom_write()
1072 default: in pnv_pec_stk_nest_xscom_write()
1094 /* All registers are read-able */ in pnv_pec_stk_pci_xscom_read()
1095 return phb->pci_regs[reg]; in pnv_pec_stk_pci_xscom_read()
1105 phb->pci_regs[reg] = val & PPC_BITMASK(0, 5); in pnv_pec_stk_pci_xscom_write()
1108 phb->pci_regs[PEC_PCI_STK_PCI_FIR] &= val; in pnv_pec_stk_pci_xscom_write()
1111 phb->pci_regs[PEC_PCI_STK_PCI_FIR] |= val; in pnv_pec_stk_pci_xscom_write()
1114 phb->pci_regs[reg] = val & PPC_BITMASK(0, 5); in pnv_pec_stk_pci_xscom_write()
1117 phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val; in pnv_pec_stk_pci_xscom_write()
1120 phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val; in pnv_pec_stk_pci_xscom_write()
1124 phb->pci_regs[reg] = val & PPC_BITMASK(0, 5); in pnv_pec_stk_pci_xscom_write()
1127 phb->pci_regs[reg] = 0; in pnv_pec_stk_pci_xscom_write()
1130 phb->pci_regs[reg] = val & PPC_BIT(0); in pnv_pec_stk_pci_xscom_write()
1136 phb->pci_regs[reg] = val & in pnv_pec_stk_pci_xscom_write()
1142 phb->pci_regs[reg] = val & (PPC_BITMASK(33, 34) | PPC_BITMASK(44, 47)); in pnv_pec_stk_pci_xscom_write()
1144 default: in pnv_pec_stk_pci_xscom_write()
1175 lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]); in pnv_phb4_set_irq()
1177 qemu_set_irq(phb->qirqs[lsi_base + irq_num], level); in pnv_phb4_set_irq()
1188 if (ds->pe_num != PHB_INVALID_PE) { in pnv_phb4_resolve_pe()
1193 rtt = ds->phb->regs[PHB_RTT_BAR >> 3]; in pnv_phb4_resolve_pe()
1195 phb_error(ds->phb, "DMA with RTT BAR disabled !"); in pnv_phb4_resolve_pe()
1201 bus_num = pci_bus_num(ds->bus); in pnv_phb4_resolve_pe()
1203 addr += 2 * PCI_BUILD_BDF(bus_num, ds->devfn); in pnv_phb4_resolve_pe()
1206 phb_error(ds->phb, "Failed to read RTT entry at 0x%"PRIx64, addr); in pnv_phb4_resolve_pe()
1213 num_PEs = ds->phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1); in pnv_phb4_resolve_pe()
1215 phb_error(ds->phb, "RTE for RID 0x%x invalid (%04x", ds->devfn, rte); in pnv_phb4_resolve_pe()
1216 rte &= num_PEs - 1; in pnv_phb4_resolve_pe()
1218 ds->pe_num = rte; in pnv_phb4_resolve_pe()
1233 phb_error(ds->phb, "Invalid #levels in TVE %d", lev); in pnv_phb4_translate_tve()
1239 phb_error(ds->phb, "Access to invalid TVE"); in pnv_phb4_translate_tve()
1248 tlb->iova = addr & 0xfffffffffffff000ull; in pnv_phb4_translate_tve()
1249 tlb->translated_addr = addr & 0x0003fffffffff000ull; in pnv_phb4_translate_tve()
1250 tlb->addr_mask = 0xfffull; in pnv_phb4_translate_tve()
1251 tlb->perm = IOMMU_RW; in pnv_phb4_translate_tve()
1270 /* TODO: Multi-level untested */ in pnv_phb4_translate_tve()
1272 lev--; in pnv_phb4_translate_tve()
1275 taddr = base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) << 3); in pnv_phb4_translate_tve()
1278 phb_error(ds->phb, "Failed to read TCE at 0x%"PRIx64, taddr); in pnv_phb4_translate_tve()
1285 phb_error(ds->phb, "Invalid indirect TCE at 0x%"PRIx64, taddr); in pnv_phb4_translate_tve()
1286 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr, in pnv_phb4_translate_tve()
1288 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d", in pnv_phb4_translate_tve()
1292 sh -= tbl_shift; in pnv_phb4_translate_tve()
1298 phb_error(ds->phb, "TCE access fault at 0x%"PRIx64, taddr); in pnv_phb4_translate_tve()
1299 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr, in pnv_phb4_translate_tve()
1301 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d", in pnv_phb4_translate_tve()
1305 tce_mask = ~((1ull << tce_shift) - 1); in pnv_phb4_translate_tve()
1306 tlb->iova = addr & tce_mask; in pnv_phb4_translate_tve()
1307 tlb->translated_addr = tce & tce_mask; in pnv_phb4_translate_tve()
1308 tlb->addr_mask = ~tce_mask; in pnv_phb4_translate_tve()
1309 tlb->perm = tce & 3; in pnv_phb4_translate_tve()
1331 phb_error(ds->phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x", in pnv_phb4_translate_iommu()
1332 ds->bus, pci_bus_num(ds->bus), ds->devfn); in pnv_phb4_translate_iommu()
1339 /* DMA or 32-bit MSI ? */ in pnv_phb4_translate_iommu()
1340 cfg = ds->phb->regs[PHB_PHB4_CONFIG >> 3]; in pnv_phb4_translate_iommu()
1343 phb_error(ds->phb, "xlate on 32-bit MSI region"); in pnv_phb4_translate_iommu()
1348 tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel]; in pnv_phb4_translate_iommu()
1352 phb_error(ds->phb, "xlate on 64-bit MSI region"); in pnv_phb4_translate_iommu()
1354 default: in pnv_phb4_translate_iommu()
1355 phb_error(ds->phb, "xlate on unsupported address 0x%"PRIx64, addr); in pnv_phb4_translate_iommu()
1360 #define TYPE_PNV_PHB4_IOMMU_MEMORY_REGION "pnv-phb4-iommu-memory-region"
1369 imrc->translate = pnv_phb4_translate_iommu; in DECLARE_INSTANCE_CHECKER()
1379 * Return the index/phb-id of a PHB4 that belongs to a
1380 * pec->stacks[stack_index] stack.
1385 int index = pec->index; in pnv_phb4_pec_get_phb_id()
1388 while (index--) { in pnv_phb4_pec_get_phb_id()
1389 offset += pecc->num_phbs[index]; in pnv_phb4_pec_get_phb_id()
1403 PnvPHB4 *phb = ds->phb; in pnv_phb4_msi_write()
1410 ds->bus, pci_bus_num(ds->bus), ds->devfn); in pnv_phb4_msi_write()
1415 if (src >= phb->xsrc.nr_irqs) { in pnv_phb4_msi_write()
1422 qemu_irq_pulse(phb->qirqs[src]); in pnv_phb4_msi_write()
1430 phb_error(ds->phb, "Invalid MSI read @ 0x%" HWADDR_PRIx, addr); in pnv_phb4_msi_read()
1431 return -1; in pnv_phb4_msi_read()
1444 QLIST_FOREACH(ds, &phb->dma_spaces, list) { in pnv_phb4_dma_find()
1445 if (ds->bus == bus && ds->devfn == devfn) { in pnv_phb4_dma_find()
1462 ds->bus = bus; in pnv_phb4_dma_iommu()
1463 ds->devfn = devfn; in pnv_phb4_dma_iommu()
1464 ds->pe_num = PHB_INVALID_PE; in pnv_phb4_dma_iommu()
1465 ds->phb = phb; in pnv_phb4_dma_iommu()
1466 snprintf(name, sizeof(name), "phb4-%d.%d-iommu", phb->chip_id, in pnv_phb4_dma_iommu()
1467 phb->phb_id); in pnv_phb4_dma_iommu()
1468 memory_region_init_iommu(&ds->dma_mr, sizeof(ds->dma_mr), in pnv_phb4_dma_iommu()
1471 address_space_init(&ds->dma_as, MEMORY_REGION(&ds->dma_mr), in pnv_phb4_dma_iommu()
1473 memory_region_init_io(&ds->msi32_mr, OBJECT(phb), &pnv_phb4_msi_ops, in pnv_phb4_dma_iommu()
1475 memory_region_init_io(&ds->msi64_mr, OBJECT(phb), &pnv_phb4_msi_ops, in pnv_phb4_dma_iommu()
1479 QLIST_INSERT_HEAD(&phb->dma_spaces, ds, list); in pnv_phb4_dma_iommu()
1481 return &ds->dma_as; in pnv_phb4_dma_iommu()
1486 PnvPhb4PecState *pec = phb->pec; in pnv_phb4_xscom_realize()
1496 snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-phb-%d", in pnv_phb4_xscom_realize()
1497 pec->chip_id, pec->index, stack_no); in pnv_phb4_xscom_realize()
1498 pnv_xscom_region_init(&phb->nest_regs_mr, OBJECT(phb), in pnv_phb4_xscom_realize()
1502 snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d", in pnv_phb4_xscom_realize()
1503 pec->chip_id, pec->index, stack_no); in pnv_phb4_xscom_realize()
1504 pnv_xscom_region_init(&phb->pci_regs_mr, OBJECT(phb), in pnv_phb4_xscom_realize()
1508 /* PHB pass-through */ in pnv_phb4_xscom_realize()
1509 snprintf(name, sizeof(name), "xscom-pec-%d.%d-phb-%d", in pnv_phb4_xscom_realize()
1510 pec->chip_id, pec->index, stack_no); in pnv_phb4_xscom_realize()
1511 pnv_xscom_region_init(&phb->phb_regs_mr, OBJECT(phb), in pnv_phb4_xscom_realize()
1514 pec_nest_base = pecc->xscom_nest_base(pec); in pnv_phb4_xscom_realize()
1515 pec_pci_base = pecc->xscom_pci_base(pec); in pnv_phb4_xscom_realize()
1518 pnv_xscom_add_subregion(pec->chip, in pnv_phb4_xscom_realize()
1520 &phb->nest_regs_mr); in pnv_phb4_xscom_realize()
1521 pnv_xscom_add_subregion(pec->chip, in pnv_phb4_xscom_realize()
1523 &phb->pci_regs_mr); in pnv_phb4_xscom_realize()
1524 pnv_xscom_add_subregion(pec->chip, in pnv_phb4_xscom_realize()
1527 &phb->phb_regs_mr); in pnv_phb4_xscom_realize()
1538 QLIST_INIT(&phb->dma_spaces); in pnv_phb4_instance_init()
1541 object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); in pnv_phb4_instance_init()
1554 snprintf(name, sizeof(name), "phb4-%d.%d-pci-io", phb->chip_id, in pnv_phb4_bus_init()
1555 phb->phb_id); in pnv_phb4_bus_init()
1556 memory_region_init(&phb->pci_io, OBJECT(phb), name, 0x10000); in pnv_phb4_bus_init()
1558 snprintf(name, sizeof(name), "phb4-%d.%d-pci-mmio", phb->chip_id, in pnv_phb4_bus_init()
1559 phb->phb_id); in pnv_phb4_bus_init()
1560 memory_region_init(&phb->pci_mmio, OBJECT(phb), name, in pnv_phb4_bus_init()
1563 pci->bus = pci_register_root_bus(dev, dev->id ? dev->id : NULL, in pnv_phb4_bus_init()
1565 &phb->pci_mmio, &phb->pci_io, in pnv_phb4_bus_init()
1568 object_property_set_int(OBJECT(pci->bus), "phb-id", phb->phb_id, in pnv_phb4_bus_init()
1570 object_property_set_int(OBJECT(pci->bus), "chip-id", phb->chip_id, in pnv_phb4_bus_init()
1573 pci_setup_iommu(pci->bus, &pnv_phb4_iommu_ops, phb); in pnv_phb4_bus_init()
1574 pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; in pnv_phb4_bus_init()
1580 XiveSource *xsrc = &phb->xsrc; in pnv_phb4_realize()
1585 phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3; in pnv_phb4_realize()
1588 snprintf(name, sizeof(name), "phb4-%d.%d-regs", phb->chip_id, in pnv_phb4_realize()
1589 phb->phb_id); in pnv_phb4_realize()
1590 memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb, in pnv_phb4_realize()
1594 if (phb->big_phb) { in pnv_phb4_realize()
1599 object_property_set_int(OBJECT(xsrc), "nr-irqs", nr_irqs, &error_fatal); in pnv_phb4_realize()
1607 phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); in pnv_phb4_realize()
1613 * Address base trigger mode (POWER10)
1615 * Trigger directly the IC ESB page
1620 uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3]; in pnv_phb4_xive_notify_abt()
1621 uint64_t data = 0; /* trigger data : don't care */ in pnv_phb4_xive_notify_abt()
1640 * trigger offset to inject a trigger on the IC. This is always in pnv_phb4_xive_notify_abt()
1652 phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", addr); in pnv_phb4_xive_notify_abt()
1660 uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3]; in pnv_phb4_xive_notify_ic()
1661 uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; in pnv_phb4_xive_notify_ic()
1674 phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", notif_port); in pnv_phb4_xive_notify_ic()
1684 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE) { in pnv_phb4_xive_notify()
1693 DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
1696 DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, TYPE_PNV_PHB, PnvPHB *),
1704 dc->realize = pnv_phb4_realize; in pnv_phb4_class_init()
1706 dc->user_creatable = false; in pnv_phb4_class_init()
1708 xfc->notify = pnv_phb4_xive_notify; in pnv_phb4_class_init()
1736 if (strcmp(name, "phb-id") == 0) { in pnv_phb4_root_bus_get_prop()
1737 value = bus->phb_id; in pnv_phb4_root_bus_get_prop()
1739 value = bus->chip_id; in pnv_phb4_root_bus_get_prop()
1757 if (strcmp(name, "phb-id") == 0) { in pnv_phb4_root_bus_set_prop()
1758 bus->phb_id = value; in pnv_phb4_root_bus_set_prop()
1760 bus->chip_id = value; in pnv_phb4_root_bus_set_prop()
1768 object_class_property_add(klass, "phb-id", "int", in pnv_phb4_root_bus_class_init()
1773 object_class_property_add(klass, "chip-id", "int", in pnv_phb4_root_bus_class_init()
1782 k->max_dev = 1; in pnv_phb4_root_bus_class_init()
1805 phb->regs[PHB_INT_NOTIFY_ADDR >> 3] & ~PHB_INT_NOTIFY_ADDR_64K; in pnv_phb4_pic_print_info()
1806 uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; in pnv_phb4_pic_print_info()
1807 bool abt = !!(phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE); in pnv_phb4_pic_print_info()
1812 phb->chip_id, phb->phb_id, in pnv_phb4_pic_print_info()
1813 offset, offset + phb->xsrc.nr_irqs - 1, in pnv_phb4_pic_print_info()
1816 xive_source_pic_print_info(&phb->xsrc, 0, buf); in pnv_phb4_pic_print_info()