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/linux-5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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/linux-5.10/arch/arc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for ARC700
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
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/linux-5.10/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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/linux-5.10/arch/parisc/include/asm/
Dropes.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm/parisc-device.h>
8 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
21 ** allocated and free'd/purged at a time might make this
33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
38 unsigned long *res_hint; /* next avail IOVP - circular search */
85 unsigned int num_ioc; /* number of on-board IOC's */
95 static inline int IS_ASTRO(struct parisc_device *d) { in IS_ASTRO() argument
96 return d->id.hversion == ASTRO_RUNWAY_PORT; in IS_ASTRO()
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/linux-5.10/arch/powerpc/kernel/
Dsetup_64.c1 // SPDX-License-Identifier: GPL-2.0-or-later
61 #include <asm/code-patching.h>
66 #include <asm/feature-fixups.h>
99 * If we boot via kdump on a non-primary thread, in setup_tlb_core_data()
101 * set up this TLB. in setup_tlb_core_data()
106 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; in setup_tlb_core_data()
110 * or e6500 tablewalk mode, or else TLB handlers in setup_tlb_core_data()
126 /* Look for ibm,smt-enabled OF option */
153 smt_option = of_get_property(dn, "ibm,smt-enabled", in check_smt_enabled()
168 /* Look for smt-enabled= cmdline option */
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/linux-5.10/arch/mips/kvm/
Dtlb.c6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
46 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
57 struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm; in kvm_mips_get_kernel_asid()
65 struct mm_struct *user_mm = &vcpu->arch.guest_user_mm; in kvm_mips_get_user_asid()
71 /* Structure defining an tlb entry data set. */
90 struct mips_coproc *cop0 = vcpu->arch.cop0; in kvm_mips_dump_guest_tlbs()
91 struct kvm_mips_tlb tlb; in kvm_mips_dump_guest_tlbs() local
98 tlb = vcpu->arch.guest_tlb[i]; in kvm_mips_dump_guest_tlbs()
[all …]
Demulate.c23 #include <asm/cpu-info.h>
46 struct kvm_vcpu_arch *arch = &vcpu->arch; in kvm_compute_return_epc()
53 return -EINVAL; in kvm_compute_return_epc()
66 arch->gprs[insn.r_format.rd] = epc + 8; in kvm_compute_return_epc()
69 nextpc = arch->gprs[insn.r_format.rs]; in kvm_compute_return_epc()
72 return -EINVAL; in kvm_compute_return_epc()
85 if ((long)arch->gprs[insn.i_format.rs] < 0) in kvm_compute_return_epc()
94 if ((long)arch->gprs[insn.i_format.rs] >= 0) in kvm_compute_return_epc()
103 arch->gprs[31] = epc + 8; in kvm_compute_return_epc()
104 if ((long)arch->gprs[insn.i_format.rs] < 0) in kvm_compute_return_epc()
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/linux-5.10/arch/openrisc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OpenRISC tlb.c
11 * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se>
12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
29 #define NO_CONTEXT -1
35 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1))
36 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1))
38 * Invalidate all TLB entries.
51 /* Determine number of sets for IMMU. */ in local_flush_tlb_all()
52 /* FIXME: Assumption is I & D nsets equal. */ in local_flush_tlb_all()
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/linux-5.10/arch/mips/mm/
Dc-octeon.c6 * Copyright (C) 2005-2007 Cavium Networks
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
34 * Octeon automatically flushes the dcache on tlb changes, so
50 * Flush local I-cache for the specified range.
83 mask = *mm_cpumask(vma->vm_mm); in octeon_flush_icache_all_cores()
139 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_range()
154 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_page()
179 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
180 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
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Dc-tx39.c1 // SPDX-License-Identifier: GPL-2.0
42 /* TX39H-style cache flush routines. */
161 if (!(cpu_context(smp_processor_id(), vma->vm_mm))) in tx39_flush_cache_range()
169 int exec = vma->vm_flags & VM_EXEC; in tx39_flush_cache_page()
170 struct mm_struct *mm = vma->vm_mm; in tx39_flush_cache_page()
194 * too difficult since stupid R4k caches do a TLB translation in tx39_flush_cache_page()
198 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { in tx39_flush_cache_page()
208 * Do indexed flush, too much work to get the (possible) TLB refills in tx39_flush_cache_page()
229 if (end - start > dcache_size) in tx39_flush_icache_range()
234 if (end - start > icache_size) in tx39_flush_icache_range()
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/linux-5.10/Documentation/x86/
Dpti.rst1 .. SPDX-License-Identifier: GPL-2.0
27 This approach helps to ensure that side-channel attacks leveraging
30 Once enabled at compile-time, it can be disabled at boot with the
31 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).
36 When PTI is enabled, the kernel manages two sets of page tables.
43 that any missed kernel->user CR3 switch will immediately crash
49 each CPU's copy of the area a compile-time-fixed virtual address.
65 Protection against side-channel attacks is important. But,
70 a. Each process now needs an order-1 PGD instead of order-0.
86 non-PTI SYSCALL entry code, so requires mapping fewer
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Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
70 allocated PASID. The driver for the device calls an IOMMU-specific API
[all …]
/linux-5.10/include/asm-generic/
Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_finish_mmu(); start and finish a mmu_gather
51 * Finish in particular will issue a (final) TLB invalidate and free
54 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
59 * - tlb_remove_table()
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/linux-5.10/drivers/parisc/
Dccio-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
9 ** (c) Copyright 2000 Hewlett-Packard Company
15 ** the I/O MMU - basically what x86 does.
17 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
18 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
19 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
21 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
24 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
[all …]
/linux-5.10/arch/parisc/include/uapi/asm/
Dpdc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
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/linux-5.10/arch/nds32/kernel/
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2005-2017 Andes Technology Corporation
10 #include <linux/dma-mapping.h>
15 #include <asm/proc-fns.h>
102 pr_info("CPU%d Features: %s\n", cpu, str); in dump_cpu_info()
106 L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE); in dump_cpu_info()
109 L1_cache_info[ICACHE].sets / 1024; in dump_cpu_info()
111 L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways, in dump_cpu_info()
115 L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE); in dump_cpu_info()
118 L1_cache_info[DCACHE].sets / 1024; in dump_cpu_info()
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/linux-5.10/drivers/misc/sgi-gru/
Dgrufault.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * FAULT HANDLER FOR GRU DETECTED TLB MISSES
7 * This file contains code that handles TLB misses within the GRU.
33 #define VTOP_INVALID -1
34 #define VTOP_RETRY -2
52 vma = find_vma(current->mm, vaddr); in gru_find_vma()
53 if (vma && vma->vm_start <= vaddr && vma->vm_ops == &gru_vm_ops) in gru_find_vma()
62 * - *gts with the mmap_lock locked for read and the GTS locked.
63 * - NULL if vaddr invalid OR is not a valid GSEG vaddr.
68 struct mm_struct *mm = current->mm; in gru_find_lock_gts()
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/linux-5.10/arch/parisc/mm/
Dfault.c37 * parisc_acctyp(unsigned int inst) --
38 * Given a PA-RISC memory access instruction, determine if the
79 * older PA-RISC platforms. The case where a block in parisc_acctyp()
87 * 01 Graphics flush write (IO space -> VM) in parisc_acctyp()
88 * 10 Graphics flush read (VM -> IO space) in parisc_acctyp()
89 * 11 Graphics flush read/write (VM <-> IO space) in parisc_acctyp()
104 * Data TLB miss fault/data page fault in parisc_acctyp()
125 * not, but I want it committed to CVS so I don't lose it :-)
128 if (tree->vm_start > addr) {
129 tree = tree->vm_avl_left;
[all …]
/linux-5.10/arch/microblaze/include/asm/
Dpgtable.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
51 * Sort of meaningless for non-VM targets.
58 #include <asm-generic/pgtable-nopmd.h>
103 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
107 * We use the hash table as an extended TLB, i.e. a cache of currently
108 * active mappings. We maintain a two-level page table tree, much
110 * management code. Low-level assembler code in hashtable.S
117 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
[all …]
/linux-5.10/arch/x86/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <asm/nospec-branch.h>
31 * TLB flushing, formerly SMP-only
57 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
64 * ASID - [0, TLB_NR_DYN_ASIDS-1]
67 * kPCID - [1, TLB_NR_DYN_ASIDS]
71 * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
91 #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
94 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
95 * for them being zero-based. Another -1 is because PCID 0 is reserved for
[all …]
Dpgtable.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <asm/tlb.h>
11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
23 void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) in paravirt_tlb_remove_table() argument
25 tlb_remove_page(tlb, table); in paravirt_tlb_remove_table()
39 return -EINVAL; in setup_userpte()
48 return -EINVAL; in setup_userpte()
53 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) in ___pte_free_tlb() argument
57 paravirt_tlb_remove_table(tlb, pte); in ___pte_free_tlb()
61 void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) in ___pmd_free_tlb() argument
[all …]
/linux-5.10/arch/sh/kernel/cpu/
Dinit.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2002 - 2009 Paul Mundt
39 * Generic wrapper for command line arguments to disable on-chip
85 * Disable support for slottable sleep instruction, non-nop in expmask_init()
87 * the memory-mapped cache array. in expmask_init()
98 /* 2nd-level cache init */
104 * Generic first-level cache init
115 * At this point we don't know whether the cache is enabled or not - a in cache_init()
120 * => before re-initialising the cache, we must do a purge of the whole in cache_init()
123 * - RPC in cache_init()
[all …]
/linux-5.10/mm/
Dmadvise.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/page-isolation.h>
26 #include <linux/backing-dev.h>
33 #include <asm/tlb.h>
38 struct mmu_gather *tlb; member
43 * Any behaviour which results in changes to the vma->vm_flags needs to
71 struct mm_struct *mm = vma->vm_mm; in madvise_behavior()
74 unsigned long new_flags = vma->vm_flags; in madvise_behavior()
90 if (vma->vm_flags & VM_IO) { in madvise_behavior()
91 error = -EINVAL; in madvise_behavior()
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/linux-5.10/arch/powerpc/include/asm/book3s/32/
Dpgtable.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm-generic/pgtable-nopmd.h>
27 * Location of the PFN in the PTE. Most 32-bit platforms use the same
29 * Platform who don't just pre-define the value so we don't override it here.
34 * The mask covered by the RPN must be a ULL on 32-bit platforms with
35 * 64-bit PTEs.
38 #define PTE_RPN_MASK (~((1ULL << PTE_RPN_SHIFT) - 1))
41 #define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1))
53 * We define 2 sets of base prot bits, one for basic pages (ie,
107 #define PGD_INDEX_SIZE (32 - PGDIR_SHIFT)
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/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dgmc_v7_0.c76 switch (adev->asic_type) { in gmc_v7_0_init_golden_registers()
124 * gmc_v7_0_init_microcode - load ucode images from disk
140 switch (adev->asic_type) { in gmc_v7_0_init_microcode()
159 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v7_0_init_microcode()
162 err = amdgpu_ucode_validate(adev->gmc.fw); in gmc_v7_0_init_microcode()
167 release_firmware(adev->gmc.fw); in gmc_v7_0_init_microcode()
168 adev->gmc.fw = NULL; in gmc_v7_0_init_microcode()
174 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
189 if (!adev->gmc.fw) in gmc_v7_0_mc_load_microcode()
190 return -EINVAL; in gmc_v7_0_mc_load_microcode()
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