book3s/32/pgtable.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm-generic/pgtable-nopmd.h>
27  * Location of the PFN in the PTE. Most 32-bit platforms use the same
29  * Platform who don't just pre-define the value so we don't override it here.
34  * The mask covered by the RPN must be a ULL on 32-bit platforms with
35  * 64-bit PTEs.
38 #define PTE_RPN_MASK	(~((1ULL << PTE_RPN_SHIFT) - 1))
41 #define PTE_RPN_MASK	(~((1UL << PTE_RPN_SHIFT) - 1))
53  * We define 2 sets of base prot bits, one for basic pages (ie,
107 #define PGD_INDEX_SIZE	(32 - PGDIR_SHIFT)
119 #define PMD_MASKED_BITS		(PTE_TABLE_SIZE - 1)
126  * The normal case is that PTEs are 32-bits and we have a 1-page
127  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
129  * For any >32-bit physical address platform, we can use the following
132  * level has 2048 entries and the second level has 512 64-bit PTE entries.
133  * -Matt
135 /* PGDIR_SHIFT determines what a top-level page table entry can map */
138 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
174  * any out-of-bounds memory accesses will hopefully be caught.
185  * of RAM.  -- Cort
189 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
199 #define MODULES_VADDR	(MODULES_END - SZ_256M)
210 	pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
213 	pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
215  * Bits in a linux-style PTE.  These match the bits in the
216  * (hardware-defined) PowerPC PTE as closely as possible.
232  * When flushing the tlb entry for a page, we also need to flush the hash
242 /* Flush an entry from the TLB/hash table */
248  * valid PTE is updated. This does -not- include set_pte_at()
249  * which nowadays only sets a new PTE.
268 "	lwz	%0, -4(%3)\n"  in pte_update()
273 "	bne-	1b"  in pte_update()
287  * 2.6 calls this without flushing the TLB entry; this is wrong
288  * for our hash-based implementation, we fix that up here.
298 		flush_hash_pages(mm->context.id, addr, ptephys, 1);  in __ptep_test_and_clear_young()
303 	__ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep)
327 	pte_update(vma->vm_mm, address, ptep, 0, set, 0);  in __ptep_set_access_flags()
342  *   -- paulus
387 	 * A read-only access is controlled by _PAGE_USER bit.  in pte_access_permitted()
498 	/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the  in __set_pte_at()
501 	 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving  in __set_pte_at()
502 	 * the hash bits instead (ie, same as the non-SMP case)  in __set_pte_at()
511 	/* Second case is 32-bit with 64-bit PTE.  In this case, we  in __set_pte_at()
514 	 * in the hash code, to pre-invalidate if the PTE was already hashed,  in __set_pte_at()
534 	/* Third case is 32-bit hash table in UP mode, we need to preserve  in __set_pte_at()