mips/mm/c-tx39.c

1 // SPDX-License-Identifier: GPL-2.0
42 /* TX39H-style cache flush routines. */
161 	if (!(cpu_context(smp_processor_id(), vma->vm_mm)))  in tx39_flush_cache_range()
169 	int exec = vma->vm_flags & VM_EXEC;  in tx39_flush_cache_page()
170 	struct mm_struct *mm = vma->vm_mm;  in tx39_flush_cache_page()
194 	 * too difficult since stupid R4k caches do a TLB translation  in tx39_flush_cache_page()
198 	if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {  in tx39_flush_cache_page()
208 	 * Do indexed flush, too much work to get the (possible) TLB refills  in tx39_flush_cache_page()
229 	if (end - start > dcache_size)  in tx39_flush_icache_range()
234 	if (end - start > icache_size)  in tx39_flush_icache_range()
258 	if (((size | addr) & (PAGE_SIZE - 1)) == 0) {  in tx39_dma_cache_wback_inv()
275 	if (((size | addr) & (PAGE_SIZE - 1)) == 0) {  in tx39_dma_cache_inv()
336 		/* TX39/H core (writethru direct-map cache) */  in tx39_cache_init()
352 		shm_align_mask		= PAGE_SIZE - 1;  in tx39_cache_init()
359 		/* TX39/H2,H3 core (writeback 2way-set-associative cache) */  in tx39_cache_init()
360 		/* board-dependent init code may set WBON */  in tx39_cache_init()
383 				       (dcache_size / current_cpu_data.dcache.ways) - 1,  in tx39_cache_init()
384 				       PAGE_SIZE - 1);  in tx39_cache_init()
395 	current_cpu_data.icache.sets =  in tx39_cache_init()
397 	current_cpu_data.dcache.sets =  in tx39_cache_init()
406 	pr_info("Primary instruction cache %ldkB, linesize %d bytes\n",  in tx39_cache_init()
408 	pr_info("Primary data cache %ldkB, linesize %d bytes\n",  in tx39_cache_init()