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/qemu/gdb-xml/
H A Ds390-cr.xml10 <reg name="cr0" bitsize="64" type="uint64" group="control"/>
11 <reg name="cr1" bitsize="64" type="uint64" group="control"/>
12 <reg name="cr2" bitsize="64" type="uint64" group="control"/>
13 <reg name="cr3" bitsize="64" type="uint64" group="control"/>
14 <reg name="cr4" bitsize="64" type="uint64" group="control"/>
15 <reg name="cr5" bitsize="64" type="uint64" group="control"/>
16 <reg name="cr6" bitsize="64" type="uint64" group="control"/>
17 <reg name="cr7" bitsize="64" type="uint64" group="control"/>
18 <reg name="cr8" bitsize="64" type="uint64" group="control"/>
19 <reg name="cr9" bitsize="64" type="uint64" group="control"/>
[all …]
/qemu/hw/misc/
H A Dallwinner-cpucfg.c36 REG_CPUS_RST_CTRL = 0x0000, /* CPUs Reset Control */
37 REG_CPU0_RST_CTRL = 0x0040, /* CPU#0 Reset Control */
38 REG_CPU0_CTRL = 0x0044, /* CPU#0 Control */
40 REG_CPU1_RST_CTRL = 0x0080, /* CPU#1 Reset Control */
41 REG_CPU1_CTRL = 0x0084, /* CPU#1 Control */
43 REG_CPU2_RST_CTRL = 0x00C0, /* CPU#2 Reset Control */
44 REG_CPU2_CTRL = 0x00C4, /* CPU#2 Control */
46 REG_CPU3_RST_CTRL = 0x0100, /* CPU#3 Reset Control */
47 REG_CPU3_CTRL = 0x0104, /* CPU#3 Control */
51 REG_GEN_CTRL = 0x0184, /* General Control */
[all …]
H A Dallwinner-h3-ccu.c2 * Allwinner H3 Clock Control Unit emulation
30 REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
31 REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
32 REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
33 REG_PLL_VE = 0x0018, /* PLL VE Control */
34 REG_PLL_DDR = 0x0020, /* PLL DDR Control */
35 REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
36 REG_PLL_GPU = 0x0038, /* PLL GPU Control */
37 REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
38 REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
[all …]
H A Da9scu.c2 * Cortex-A9MPCore Snoop Control Unit (SCU) emulation.
26 case 0x00: /* Control */ in a9_scu_read()
27 return s->control; in a9_scu_read()
38 case 0x50: /* SCU Access Control Register */ in a9_scu_read()
39 case 0x54: /* SCU Non-secure Access Control Register */ in a9_scu_read()
54 case 0x00: /* Control */ in a9_scu_write()
55 s->control = value & 1; in a9_scu_write()
59 case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */ in a9_scu_write()
69 case 0x50: /* SCU Access Control Register */ in a9_scu_write()
70 case 0x54: /* SCU Non-secure Access Control Register */ in a9_scu_write()
[all …]
H A Dallwinner-sid.c35 REG_PRCTL = 0x40, /* Control */
52 case REG_PRCTL: /* Control */ in allwinner_sid_read()
53 val = s->control; in allwinner_sid_read()
77 case REG_PRCTL: /* Control */ in allwinner_sid_write()
78 s->control = val; in allwinner_sid_write()
80 if ((s->control & REG_PRCTL_OP_LOCK) && in allwinner_sid_write()
81 (s->control & REG_PRCTL_WRITE)) { in allwinner_sid_write()
82 uint32_t id = s->control >> 16; in allwinner_sid_write()
88 s->control &= ~REG_PRCTL_WRITE; in allwinner_sid_write()
115 s->control = 0; in allwinner_sid_reset()
[all …]
H A Dexynos4210_pmu.c70 /* Sets control options for CENTRAL_SEQ */
77 #define HDMI_PHY_CONTROL 0x0700 /* HDMI PHY control register */
78 #define USBDEVICE_PHY_CONTROL 0x0704 /* USB Device PHY control register */
79 #define USBHOST_PHY_CONTROL 0x0708 /* USB HOST PHY control register */
80 #define DAC_PHY_CONTROL 0x070C /* DAC control register */
81 #define MIPI_PHY0_CONTROL 0x0710 /* MIPI PHY control register */
82 #define MIPI_PHY1_CONTROL 0x0714 /* MIPI PHY control register */
83 #define ADC_PHY_CONTROL 0x0718 /* TS-ADC control register */
84 #define PCIe_PHY_CONTROL 0x071C /* TS-PCIe control register */
85 #define SATA_PHY_CONTROL 0x0720 /* TS-SATA control register */
[all …]
H A Dallwinner-a10-ccm.c2 * Allwinner A10 Clock Control Module emulation
33 REG_PLL1_CFG = 0x0000, /* PLL1 Control */
35 REG_PLL2_CFG = 0x0008, /* PLL2 Control */
37 REG_PLL3_CFG = 0x0010, /* PLL3 Control */
38 REG_PLL4_CFG = 0x0018, /* PLL4 Control */
39 REG_PLL5_CFG = 0x0020, /* PLL5 Control */
41 REG_PLL6_CFG = 0x0028, /* PLL6 Control */
43 REG_PLL7_CFG = 0x0030, /* PLL7 Control */
46 REG_PLL8_CFG = 0x0040, /* PLL8 Control */
47 REG_OSC24M_CFG = 0x0050, /* OSC24M Control */
/qemu/hw/timer/
H A Darm_mptimer.c58 qemu_set_irq(tb->irq, tb->status && (tb->control & 4)); in timerblock_update_irq()
62 static inline uint32_t timerblock_scale(uint32_t control) in timerblock_scale() argument
64 return (((control >> 8) & 0xff) + 1) * 10; in timerblock_scale()
69 uint32_t control, uint64_t *count) in timerblock_set_count() argument
74 if ((control & 3) == 3 && (control & 0xff00) == 0 && *count == 0) { in timerblock_set_count()
82 uint32_t control, uint32_t load) in timerblock_run() argument
84 if ((control & 1) && ((control & 0xff00) || load != 0)) { in timerblock_run()
85 ptimer_run(timer, !(control & 2)); in timerblock_run()
95 if ((tb->control & 2) && (tb->control & 0xff00) == 0 && in timerblock_tick()
112 case 8: /* Control. */ in timerblock_read()
[all …]
H A Dcmsdk-apb-dualtimer.c35 FIELD(CONTROL, ONESHOT, 0, 1)
36 FIELD(CONTROL, SIZE, 1, 1)
37 FIELD(CONTROL, PRESCALE, 2, 2)
38 FIELD(CONTROL, INTEN, 5, 1)
39 FIELD(CONTROL, MODE, 6, 1)
40 FIELD(CONTROL, ENABLE, 7, 1)
86 return m->intstatus && (m->control & R_CONTROL_INTEN_MASK); in cmsdk_dualtimermod_intstatus()
111 /* Return the divisor set by the current CONTROL.PRESCALE value */ in cmsdk_dualtimermod_divisor()
112 switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) { in cmsdk_dualtimermod_divisor()
128 /* Handle a write to the CONTROL register */ in cmsdk_dualtimermod_write_control()
[all …]
H A Darmv7m_systick.c39 if (s->control & SYSTICK_CLKSOURCE) { in systick_set_period_from_clock()
52 s->control |= SYSTICK_COUNTFLAG; in systick_timer_tick()
53 if (s->control & SYSTICK_TICKINT) { in systick_timer_tick()
78 case 0x0: /* SysTick Control and Status. */ in systick_read()
79 val = s->control; in systick_read()
80 s->control &= ~SYSTICK_COUNTFLAG; in systick_read()
138 case 0x0: /* SysTick Control and Status. */ in systick_write()
148 oldval = s->control; in systick_write()
149 s->control &= 0xfffffff8; in systick_write()
150 s->control |= value & 7; in systick_write()
[all …]
H A Da9gtimer.c65 uint64_t prescale = extract32(s->control, R_CONTROL_PRESCALER_SHIFT, in a9_gtimer_get_conv()
92 if ((s->control & R_CONTROL_TIMER_ENABLE) && in a9_gtimer_update()
93 (gtb->control & R_CONTROL_COMP_ENABLE)) { in a9_gtimer_update()
98 if (gtb->control & R_CONTROL_AUTO_INCREMENT && gtb->inc) { in a9_gtimer_update()
113 gtb->status && (gtb->control & R_CONTROL_IRQ_ENABLE)); in a9_gtimer_update()
123 if (s->control & R_CONTROL_TIMER_ENABLE) { in a9_gtimer_update()
157 ret = s->control | gtb->control; in a9_gtimer_read()
200 if (s->control & R_CONTROL_TIMER_ENABLE) { in a9_gtimer_write()
207 a9_gtimer_update(s, (value ^ s->control) & R_CONTROL_NEEDS_SYNC); in a9_gtimer_write()
208 gtb->control = value & R_CONTROL_BANKED; in a9_gtimer_write()
[all …]
H A Dallwinner-a10-pit.c52 return s->control[index]; in a10_pit_read()
87 prescaler = 1 << extract32(s->control[index], 4, 3); in a10_pit_set_freq()
88 source = extract32(s->control[index], 2, 2); in a10_pit_set_freq()
120 s->control[index] = value; in a10_pit_write()
123 if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { in a10_pit_write()
126 if (s->control[index] & AW_A10_PIT_TIMER_EN) { in a10_pit_write()
128 if (s->control[index] & AW_A10_PIT_TIMER_MODE) { in a10_pit_write()
205 VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR),
228 s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; in a10_pit_reset()
249 if (s->control[i] & AW_A10_PIT_TIMER_EN) { in a10_pit_timer_cb()
[all …]
/qemu/include/hw/i2c/
H A Dnpcm7xx_smbus.h48 * @cst: The control status register.
49 * @cst2: The control status register 2.
50 * @cst3: The control status register 3.
51 * @ctl1: The control register 1.
52 * @ctl2: The control register 2.
53 * @ctl3: The control register 3.
54 * @ctl4: The control register 4.
55 * @ctl5: The control register 5.
59 * @fif_ctl: The FIFO control register.
60 * @fif_cts: The FIFO control status register.
[all …]
/qemu/ui/
H A Dcurses_keys.h49 /* curses won't detect a Control + Alt + 1, so use Alt + 1 */
184 ['Q' - '@'] = 16 | CNTRL, /* Control + q */
185 ['W' - '@'] = 17 | CNTRL, /* Control + w */
186 ['E' - '@'] = 18 | CNTRL, /* Control + e */
187 ['R' - '@'] = 19 | CNTRL, /* Control + r */
188 ['T' - '@'] = 20 | CNTRL, /* Control + t */
189 ['Y' - '@'] = 21 | CNTRL, /* Control + y */
190 ['U' - '@'] = 22 | CNTRL, /* Control + u */
191 /* Control + i collides with Tab */
192 ['O' - '@'] = 24 | CNTRL, /* Control + o */
[all …]
/qemu/hw/net/
H A De1000_regs.h46 #define E1000_FCRTV 0x05F40 /* Flow Control Refresh Timer Value - RW */
51 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
53 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
59 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
65 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
84 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
85 #define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
102 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
111 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
131 #define E1000_GCR2 0x05B64 /* 3GIO Control Register 2 */
[all …]
H A De1000x_regs.h121 #define E1000_CTRL 0x00000 /* Device Control - RW */
122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
124 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
126 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
128 #define E1000_MDIC 0x00020 /* MDI Control - RW */
129 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
130 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
131 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
132 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
139 #define E1000_RCTL 0x00100 /* RX Control - RW */
[all …]
/qemu/pc-bios/s390-ccw/
H A Dcio.h17 * path management control word
43 u32 mbfc:1; /* measurement block format control */
73 /* Function Control */
78 /* Activity Control */
87 /* Status Control */
118 struct pmcw pmcw; /* path management control word */
238 u32 key:4; /* flags, like key, suspend control, etc. */
239 u32 spnd:1; /* suspend control */
241 u32 mod:1; /* modification control */
242 u32 sync:1; /* synchronize control */
[all …]
/qemu/include/hw/net/
H A Dallwinner-sun8i-emac.h69 uint32_t mii_cr; /**< Control */
80 uint32_t basic_ctl0; /**< Basic Control 0 */
81 uint32_t basic_ctl1; /**< Basic Control 1 */
86 uint32_t rx_ctl0; /**< Receive Control 0 */
87 uint32_t rx_ctl1; /**< Receive Control 1 */
91 uint32_t tx_ctl0; /**< Transmit Control 0 */
92 uint32_t tx_ctl1; /**< Transmit Control 1 */
95 uint32_t tx_flowctl; /**< Transmit Flow Control */
/qemu/hw/intc/
H A Dompic.c45 uint32_t control; member
62 /* We can only write to control control, write control + update status */ in ompic_read()
64 return s->cpus[src_cpu].control; in ompic_read()
74 /* We can only write to control control, write control + update status */ in ompic_write()
78 s->cpus[src_cpu].control = data; in ompic_write()
141 VMSTATE_UINT32(control, OR1KOMPICCPUState),
/qemu/rust/hw/char/pl011/src/
H A Dregisters.rs6 //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
48 /// line control register (data frame format)
69 /// DMA control Register
151 /// This has the usual inbound RS232 modem-control signals, plus flags
196 /// Line Control Register, `UARTLCR_H`
237 /// `EPS` "Even parity select", field of [Line Control
246 /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control
258 /// `WLEN` Word length, field of [Line Control register](LineControl).
273 /// Control Register, `UARTCR`
275 /// The `UARTCR` register is the control register. It contains various
[all …]
/qemu/hw/char/
H A Dparallel.c66 * These are the definitions for the Printer Control Register
108 if ((s->control & PARA_CTR_STROBE) == 0) in parallel_ioport_write_sw()
113 if (s->control & PARA_CTR_INTEN) { in parallel_ioport_write_sw()
119 s->control = val; in parallel_ioport_write_sw()
152 if (s->control == val) in parallel_ioport_write_hw()
156 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { in parallel_ioport_write_hw()
167 s->control = val; in parallel_ioport_write_hw()
170 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) in parallel_ioport_write_hw()
185 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) in parallel_ioport_write_hw()
212 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { in parallel_ioport_eppdata_write_hw2()
[all …]
/qemu/target/arm/tcg/
H A Dtranslate-m-nocp.c96 * End the TB, because we have updated FP control bits, in trans_VLLDM_VLSTM()
134 sfpa = load_cpu_field(v7m.control[M_REG_S]); in trans_VSCCLRM()
294 /* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */ in gen_branch_fpInactive()
297 fpca = load_cpu_field(v7m.control[M_REG_S]); in gen_branch_fpInactive()
381 TCGv_i32 sfpa, control; in gen_M_fp_sysreg_write() local
383 * Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes in gen_M_fp_sysreg_write()
389 control = load_cpu_field(v7m.control[M_REG_S]); in gen_M_fp_sysreg_write()
390 tcg_gen_deposit_i32(control, control, sfpa, in gen_M_fp_sysreg_write()
392 store_cpu_field(control, v7m.control[M_REG_S]); in gen_M_fp_sysreg_write()
474 TCGv_i32 control, sfpa, fpscr; in gen_M_fp_sysreg_read() local
[all …]
/qemu/hw/arm/
H A Dbcm2836.c40 object_initialize_child(obj, "control", &s->control, in bcm283x_base_init()
120 if (!sysbus_realize(SYS_BUS_DEVICE(&s_base->control), errp)) { in bcm2836_realize()
124 sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc->ctrl_base); in bcm2836_realize()
127 qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-irq", 0)); in bcm2836_realize()
129 qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-fiq", 0)); in bcm2836_realize()
149 qdev_connect_gpio_out_named(DEVICE(&s_base->control), "irq", n, in bcm2836_realize()
151 qdev_connect_gpio_out_named(DEVICE(&s_base->control), "fiq", n, in bcm2836_realize()
156 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpnsirq", n)); in bcm2836_realize()
158 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntvirq", n)); in bcm2836_realize()
160 qdev_get_gpio_in_named(DEVICE(&s_base->control), "cnthpirq", n)); in bcm2836_realize()
[all …]
/qemu/hw/i2c/
H A Domap_i2c.c51 uint16_t control; member
77 if ((s->control >> 2) & 1) { /* RM */ in omap_i2c_fifo_run()
78 if ((s->control >> 1) & 1) { /* STP */ in omap_i2c_fifo_run()
80 s->control &= ~(1 << 1); /* STP */ in omap_i2c_fifo_run()
83 } else if ((s->control >> 9) & 1) { /* TRX */ in omap_i2c_fifo_run()
95 if ((s->control >> 9) & 1) { /* TRX */ in omap_i2c_fifo_run()
108 s->control &= ~(1 << 10); /* MST */ in omap_i2c_fifo_run()
121 if ((s->control >> 1) & 1) { /* STP */ in omap_i2c_fifo_run()
123 s->control &= ~(1 << 1); /* STP */ in omap_i2c_fifo_run()
128 s->control &= ~(1 << 10); /* MST */ in omap_i2c_fifo_run()
[all …]
/qemu/include/qemu/
H A Dcoroutine-core.h22 * rather than callbacks, for operations that need to give up control while
74 * Use qemu_coroutine_enter() to actually transfer control to the coroutine.
80 * Transfer control to a coroutine
85 * Transfer control to a coroutine if it's not active (i.e. part of the call
91 * Transfer control to a coroutine and associate it with ctx
96 * Transfer control back to a coroutine's caller
127 * coroutine is currently executing code since it may have transferred control
143 * Locks the mutex. If the lock cannot be taken immediately, control is

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