hw/net/e1000x_regs.h

121 #define E1000_CTRL     0x00000  /* Device Control - RW */
122 #define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
124 #define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
126 #define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
128 #define E1000_MDIC     0x00020  /* MDI Control - RW */
129 #define E1000_SCTL     0x00024  /* SerDes Control - RW */
130 #define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
131 #define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
132 #define E1000_FCT      0x00030  /* Flow Control Type - RW */
139 #define E1000_RCTL     0x00100  /* RX Control - RW */
140 #define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
141 #define E1000_TCTL     0x00400  /* TX Control - RW */
142 #define E1000_TCTL_EXT 0x00404  /* Extended TX Control - RW */
144 #define E1000_LEDCTL   0x00E00  /* LED Control - RW */
145 #define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
147 #define E1000_FLMNGCTL     0x01018 /* MNG Flash Control */
150 #define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
152 #define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
154 #define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
186 #define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
227 #define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
228 #define E1000_RFCTL    0x05008  /* Receive Filter Control*/
238 #define E1000_WUC      0x05800  /* Wakeup Control - RW */
239 #define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
241 #define E1000_MANC     0x05820  /* Management Control - RW */
252 #define E1000_MANC2H     0x05860 /* Management Control To Host - RW */
255 #define E1000_GCR       0x05B00 /* PCI-Ex Control */
257 #define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
258 #define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
259 #define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
260 #define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
270 #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
271 #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
286 #define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
469 /* Receive Control */
505 #define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
530 /* Device Control */
573 #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
574 #define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
589 /* EEPROM/Flash Control */
628 /* MDI Control */
706 /* PCI Express Control */
707 /* 3GIO Control Register - GCR (0x05B00; RW) */
743 /* Transmit Control */
827 /* Receive Checksum Control bits */
919 /* Management Control */
957 /* FACTPS Control */