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Searched +full:cfi +full:- +full:flash (Results 1 – 17 of 17) sorted by relevance

/qemu/hw/block/
H A Dpflash_cfi01.c2 * CFI parallel flash with Intel command set emulation
24 * - flash read
25 * - flash write
26 * - flash ID read
27 * - sector erase
28 * - CFI queries
31 * It does not support flash interleaving
41 #include "hw/block/flash.h"
42 #include "hw/qdev-properties.h"
43 #include "hw/qdev-properties-system.h"
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H A Dpflash_cfi02.c2 * CFI parallel flash with AMD command set emulation
23 * - flash read
24 * - flash write
25 * - flash ID read
26 * - sector erase
27 * - chip erase
28 * - unlock bypass command
29 * - CFI queries
31 * It does not support flash interleaving.
37 #include "hw/block/flash.h"
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/qemu/tests/qtest/
H A Dpflash-cfi02-test.c2 * QTest testcase for parallel flash with AMD command set
7 * See the COPYING file in the top-level directory.
15 * a pflash drive. This enables us to test some flash configurations, but not
16 * all. In particular, we're limited to a 16-bit wide flash device.
20 #define BASE_ADDR (0x100000000ULL - MP_FLASH_SIZE_MAX)
25 /* Use a newtype to keep flash addresses separate from byte addresses. */
90 return (uint64_t)-1; in device_mask()
98 if (c->bank_width == 8) { in bank_mask()
99 return (uint64_t)-1; in bank_mask()
101 return (1ULL << (c->bank_width * 8)) - 1ULL; in bank_mask()
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/qemu/include/hw/block/
H A Dflash.h4 /* NOR flash devices */
11 #define TYPE_PFLASH_CFI01 "cfi.pflash01"
30 #define TYPE_PFLASH_CFI02 "cfi.pflash02"
49 #define TYPE_M25P80 "m25p80-generic"
/qemu/docs/system/riscv/
H A Dvirt.rst8 real-world hardware.
11 -----------------
17 * Platform-Level Interrupt Controller (PLIC)
18 * CFI parallel NOR flash memory
22 * 8 virtio-mmio transport devices
31 ----------------------------------
34 which it passes to the guest, if there is no ``-dtb`` option. This provides
39 If users want to provide their own DTB, they can use the ``-dtb`` option.
42 * The number of subnodes of the /cpus node should match QEMU's ``-smp`` option
43 * The /memory reg size should match QEMU’s selected ram_size via ``-m``
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/qemu/docs/system/ppc/
H A Dppce500.rst8 -----------------
19 * Power-off functionality via one GPIO pin
26 ----------------------------------
29 which it passes to the guest, if there is no ``-dtb`` option. This provides
33 If users want to provide their own DTB, they can use the ``-dtb`` option.
36 * The number of subnodes under /cpus node should match QEMU's ``-smp`` option
37 * The /memory reg size should match QEMU’s selected ram_size via ``-m``
39 Both ``qemu-system-ppc`` and ``qemu-system-ppc64`` provide emulation for the
40 following 32-bit PowerPC CPUs:
45 Additionally ``qemu-system-ppc64`` provides support for the following 64-bit
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/qemu/pc-bios/dtb/
H A Dpetalogix-ml605.dts5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = < 0x01 >;
12 #size-cells = < 0x01 >;
22 ethernet0 = "/axi/axi-ethernet@82780000";
28 stdout-path = "/axi/serial@83e00000";
32 #address-cells = < 0x01 >;
34 #size-cells = < 0x00 >;
37 clock-frequency = < 0xbebc200 >;
38 compatible = "xlnx,microblaze-8.10.a";
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H A Dpetalogix-s3adsp1800.dts5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = <0x01>;
12 #size-cells = <0x01>;
23 stdout-path = "/plb/serial@84000000";
27 #address-cells = <0x01>;
28 #size-cells = <0x00>;
32 clock-frequency = <0x3b9aca0>;
33 compatible = "xlnx,microblaze-7.10.d";
34 d-cache-baseaddr = <0x90000000>;
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H A Dcanyonlands.dts4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
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/qemu/docs/interop/
H A Dfirmware.json1 # -*- Mode: Python -*-
11 # later. See the COPYING file in the top-level directory.
18 'member-name-exceptions': [
25 # Lists the firmware-OS interface types provided by various firmware
32 # 1275-1994 standard. Examples for firmware projects that
35 # @uboot: Firmware interface defined by the U-Boot project.
51 # @flash: The firmware executable and its accompanying NVRAM file are to
63 'data' : [ 'flash', 'kernel', 'memory' ] }
71 # @aarch64: 64-bit Arm.
73 # @arm: 32-bit Arm.
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/qemu/hw/loongarch/
H A Dvirt-fdt-build.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include "qemu/error-report.h"
7 #include "qemu/guest-random.h"
10 #include "hw/core/sysbus-fdt.h"
14 #include "hw/pci-host/gpex.h"
15 #include "hw/pci-host/ls7a.h"
25 ms->fdt = create_device_tree(&lvms->fdt_size); in create_fdt()
26 if (!ms->fdt) { in create_fdt()
32 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", in create_fdt()
33 "linux,dummy-loongson3"); in create_fdt()
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/qemu/hw/arm/
H A Dvirt.c2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
57 #include "qemu/error-report.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/virtio/virtio-pci.h"
61 #include "hw/core/sysbus-fdt.h"
62 #include "hw/platform-bus.h"
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/qemu/hw/net/
H A De1000x_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
115 * RW - register is both readable and writable
116 * RO - register is read only
117 * WO - register is write only
118 * R/clr - register is read only and is cleared when read
119 * A - register array
121 #define E1000_CTRL 0x00000 /* Device Control - RW */
122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
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/qemu/hw/riscv/
H A Dvirt.c2 * QEMU RISC-V VirtIO Board
6 * RISC-V machine with 16550a UART and VirtIO MMIO
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial-mm.h"
32 #include "hw/core/sysbus-fdt.h"
36 #include "hw/riscv/riscv-iommu-bits.h"
46 #include "hw/platform-bus.h"
55 #include "hw/pci-host/gpex.h"
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/qemu/hw/ppc/
H A De500.c2 * QEMU PowerPC e500-based platforms
20 #include "qemu/guest-random.h"
24 #include "e500-ccsr.h"
26 #include "qemu/config-file.h"
27 #include "hw/block/flash.h"
28 #include "hw/char/serial-mm.h"
30 #include "system/block-backend-io.h"
40 #include "hw/qdev-properties.h"
44 #include "qemu/host-utils.h"
46 #include "hw/pci-host/ppce500.h"
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/qemu/
H A DMAINTAINERS10 consult qemu-devel and not any specific individual privately.
23 W: Web-page with status/info
59 ------------------------------
63 L: qemu-devel@nongnu.org
72 R: Philippe Mathieu-Daudé <philmd@linaro.org>
75 F: docs/devel/build-environment.rst
76 F: docs/devel/code-of-conduct.rst
78 F: docs/devel/conflict-resolution.rst
80 F: docs/devel/submitting-a-patch.rst
81 F: docs/devel/submitting-a-pull-request.rst
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/qemu/tests/data/qobject/
H A Dqdict.txt1 00-INDEX: 333
55 3.Early-stage: 9993
56 3w-9xxx.c: 77318
57 3w-9xxx.h: 26357
58 3w-xxxx.c: 85227
59 3w-xxxx.h: 16846
71 4level-fixup.h: 1028
110 6xx-suspend.S: 1086
148 8250-platform.c: 1091
161 83xx-512x-pci.txt: 1323
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