a\-display (full) in projects: linux-6.15

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/linux-6.15/drivers/gpu/drm/i915/display/
D	intel_cmtg.c	1 // SPDX-License-Identifier: MIT 24 * The CMTG is a timing generator that runs in parallel to transcoders timing 25 * generators (TG) to provide a synchronization mechanism where CMTG acts as 34 * - Dual eDP: The CMTG can be used to keep two eDP TGs in sync when on a 37 * - Single eDP as secondary: It is also possible to use a single eDP 39 * allow a flow that would not require a modeset on the existing eDP when a 40 * new eDP is added for a dual eDP configuration with CMTG. 42 * - DC6v: In DC6v, the transcoder might be off but the CMTG keeps running to 47 * we disable it in case we inherit a display configuration with it enabled. 57 * Xe2_LPD adds a second CMTG that can be used for dual eDP async mode. [all …]
D	intel_combo_phy.c	1 // SPDX-License-Identifier: MIT 18 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ 34 .name = "0.85V dot0 (low-voltage)", 56 icl_get_procmon_ref_values(struct intel_display display, enum phy phy) in icl_get_procmon_ref_values() argument 60 val = intel_de_read(display, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values() 78 static void icl_set_procmon_ref_values(struct intel_display display, in icl_set_procmon_ref_values() argument 83 procmon = icl_get_procmon_ref_values(display, phy); in icl_set_procmon_ref_values() 85 intel_de_rmw(display, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values() 86 (0xff << 16) \| 0xff, procmon->dw1); in icl_set_procmon_ref_values() 88 intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values() [all …]
D	intel_fifo_underrun.c	4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 41 * The i915 driver checks for display fifo underruns using the interrupt signals 43 * debug display issues, especially watermark settings. 47 * occurrence until the next modeset on a given pipe. 49 * Note that underrun detection on gmch platforms is a bit more ugly since there 58 static bool ivb_can_enable_err_int(struct intel_display display) in ivb_can_enable_err_int() argument 60 struct drm_i915_private dev_priv = to_i915(display->drm); in ivb_can_enable_err_int() 64 lockdep_assert_held(&dev_priv->irq_lock); in ivb_can_enable_err_int() 66 for_each_pipe(display, pipe) { in ivb_can_enable_err_int() [all …]
D	intel_cdclk.c	2 * Copyright © 2006-2017 Intel Corporation 4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 55 * The display engine uses several different clocks to do its work. There 58 * are the core display clock (CDCLK) and RAWCLK. 60 * CDCLK clocks most of the display pipe logic, and thus its frequency 66 * to minimize power consumption for a given display configuration. 67 * Typically changes to the CDCLK frequency require all the display pipes 77 * - We have the CDCLK PLL, which generates an output clock based on a 78 * reference clock and a ratio parameter. [all …]
D	intel_dkl_phy.c	1 // SPDX-License-Identifier: MIT 14 * intel_dkl_phy_init - initialize Dekel PHY 15 * @display: display device instance 17 void intel_dkl_phy_init(struct intel_display display) in intel_dkl_phy_init() argument 19 spin_lock_init(&display->dkl.phy_lock); in intel_dkl_phy_init() 23 dkl_phy_set_hip_idx(struct intel_display display, struct intel_dkl_phy_reg reg) in dkl_phy_set_hip_idx() argument 27 drm_WARN_ON(display->drm, tc_port < TC_PORT_1 \|\| tc_port >= I915_MAX_TC_PORTS); in dkl_phy_set_hip_idx() 29 intel_de_write(display, in dkl_phy_set_hip_idx() 35 * intel_dkl_phy_read - read a Dekel PHY register 36 * @display: intel_display device instance [all …]
D	intel_display_power_well.c	1 // SPDX-License-Identifier: MIT 49 void (sync_hw)(struct intel_display display, 53 * interrupts located on the well). Called after the 0->1 refcount 56 void (enable)(struct intel_display display, 60 * the 1->0 refcount transition. 62 void (disable)(struct intel_display display, 65 bool (is_enabled)(struct intel_display display, 72 return &power_well->desc->instances->list[power_well->instance_idx]; in i915_power_well_instance() 76 lookup_power_well(struct intel_display *display, in lookup_power_well() argument 81 for_each_power_well(display, power_well) in lookup_power_well() [all …]
D	intel_lpe_audio.c	4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> 34 * Atom platforms (e.g. valleyview and cherryTrail) integrates a DMA-based 39 * The interface is handled by a separate standalone driver maintained in the 41 * subsystems, a bridge is setup between the hdmi-lpe-audio and i915: 42 * 1. Create a platform device to share MMIO/IRQ resources 45 * the hdmi-lpe-audio driver probes the lpe audio device and creates a new 50 * uninstall the hdmi-lpe-audio driver before uninstalling i915 module, 51 * otherwise we might run into use-after-free issues after i915 removes the [all …]
D	intel_dpll_mgr.c	2 * Copyright © 2006-2016 Intel Corporation 4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 44 * DOC: Display PLLs 46 * Display PLLs used for driving outputs vary by platform. While some have 47 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL 48 * from a pool. In the latter scenario, it is possible that multiple pipes 49 * share a PLL if their configurations match. 51 * This file provides an abstraction over display PLLs. The function 53 * users of a PLL are tracked and that tracking is integrated with the atomic [all …]
D	intel_dmc.c	4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 38 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 39 * engine to save and restore the state of display engine when it enter into 40 * low-power state and comes back to normal. 43 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firm… 55 struct intel_display display; member 73 static struct intel_dmc display_to_dmc(struct intel_display display) in display_to_dmc() argument 75 return display->dmc.dmc; in display_to_dmc() 78 static const char dmc_firmware_param(struct intel_display *display) in dmc_firmware_param() argument [all …]
D	intel_display_power.c	1 /* SPDX-License-Identifier: MIT / 33 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 37 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 201 static bool __intel_display_power_is_enabled(struct intel_display display, in __intel_display_power_is_enabled() argument 207 if (pm_runtime_suspended(display->drm->dev)) in __intel_display_power_is_enabled() 212 for_each_power_domain_well_reverse(display, power_well, domain) { in __intel_display_power_is_enabled() 226 * intel_display_power_is_enabled - check for a power domain 227 * @display: display device instance 236 * threads can't disable the power well while the caller tries to read a few 242 bool intel_display_power_is_enabled(struct intel_display *display, in intel_display_power_is_enabled() argument [all …]
D	intel_display.c	2 * Copyright © 2006-2007 Intel Corporation 4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 27 #include <linux/dma-resv.h> 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/display/drm_dp_tunnel.h> 161 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock() 175 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll() 176 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll() 178 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll() [all …]
D	intel_display_reg_defs.h	1 /* SPDX-License-Identifier: MIT */ 11 #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset) 18 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) argument 19 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) argument 20 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) argument 21 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) argument 22 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) argument 23 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) argument 25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument 26 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) argument [all …]
D	vlv_dsi_regs.h	1 /* SPDX-License-Identifier: MIT / 14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument 16 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) / ports A and C only / argument 17 #define _MMIO_MIPI(base, port, a, c) _MMIO((base) + _MIPI_PORT(port, a, c)) argument 47 #define DPI_ENABLE (1 << 31) / A + C / 54 #define DITHERING_ENABLE (1 << 25) / A + C / 75 #define TEARING_EFFECT_DELAY (1 << 4) / A + C / 76 #define TEARING_EFFECT_SHIFT 2 / A + C / 93 / MIPI DSI Controller and D-PHY registers */ 97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument [all …]
D	intel_crt.c	2 * Copyright © 2006-2007 Intel Corporation 4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 91 bool intel_crt_port_enabled(struct intel_display display, in intel_crt_port_enabled() argument 94 struct drm_i915_private dev_priv = to_i915(display->drm); in intel_crt_port_enabled() 97 val = intel_de_read(display, adpa_reg); in intel_crt_port_enabled() 111 struct intel_display *display = to_intel_display(encoder); in intel_crt_get_hw_state() local 116 wakeref = intel_display_power_get_if_enabled(display, in intel_crt_get_hw_state() 117 encoder->power_domain); in intel_crt_get_hw_state() 121 ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); in intel_crt_get_hw_state() [all …]
D	vlv_dsi.c	4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 89 struct intel_display display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty() local 95 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), in vlv_dsi_wait_for_fifo_empty() 97 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty() 100 static void write_data(struct intel_display display, in write_data() argument 109 for (j = 0; j < min_t(u32, len - i, 4); j++) in write_data() 112 intel_de_write(display, reg, val); in write_data() 116 static void read_data(struct intel_display *display, in read_data() argument 123 u32 val = intel_de_read(display, reg); in read_data() [all …]
D	intel_frontbuffer.c	4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 33 * To be able to do so we track frontbuffers using a bitmask for all possible 37 * and when the frontbuffer is exchanged with a flip. Subsystems interested in 42 * On a high level there are two types of powersaving features. The first one 43 * work like a special cache (FBC and PSR) and are interested when they should 51 * The other type of display power saving feature only cares about busyness 74 * frontbuffer_flush - flush frontbuffer 89 struct intel_display *display = &i915->display; in frontbuffer_flush() local 92 spin_lock(&i915->display.fb_tracking.lock); in frontbuffer_flush() [all …]
D	hsw_ips.c	1 // SPDX-License-Identifier: MIT 18 struct intel_display display = to_intel_display(crtc_state); in hsw_ips_enable() local 19 struct intel_crtc crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_ips_enable() 20 struct drm_i915_private i915 = to_i915(crtc->base.dev); in hsw_ips_enable() 23 if (!crtc_state->ips_enabled) in hsw_ips_enable() 27 We can only enable IPS after we enable a plane and wait for a vblank in hsw_ips_enable() 29 * a vblank wait. in hsw_ips_enable() 31 drm_WARN_ON(display->drm, in hsw_ips_enable() 32 !(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); in hsw_ips_enable() 36 if (display->ips.false_color) in hsw_ips_enable() [all …]
D	intel_gmbus.c	3 * Copyright © 2006-2008,2010 Intel Corporation 6 * Permission is hereby granted, free of charge, to any person obtaining a 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 27 * Chris Wilson <chris@chris-wilson.co.uk> 31 #include <linux/i2c-algo-bit.h> 34 #include <drm/display/drm_hdcp_helper.h> 51 struct intel_display display; member 152 static const struct gmbus_pin get_gmbus_pin(struct intel_display display, in get_gmbus_pin() argument 155 struct drm_i915_private i915 = to_i915(display->drm); in get_gmbus_pin() 177 } else if (DISPLAY_VER(display) == 9) { in get_gmbus_pin() [all …]
D	intel_display_driver.c	1 // SPDX-License-Identifier: MIT 3 * Copyright © 2022-2023 Intel Corporation 5 * High level display driver entry points. This is a layer between top level 6 * driver code and low level display functionality; no low level display code or 12 #include <drm/display/drm_dp_mst_helper.h> 67 * apple-gmux is needed on dual GPU MacBook Pro in intel_display_driver_probe_defer() 73 /* If the LCD panel has a privacy-screen, wait for it / in intel_display_driver_probe_defer() 74 privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL); in intel_display_driver_probe_defer() 75 if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER) in intel_display_driver_probe_defer() 83 void intel_display_driver_init_hw(struct intel_display display) in intel_display_driver_init_hw() argument [all …]
D	intel_vga.c	1 // SPDX-License-Identifier: MIT 17 static i915_reg_t intel_vga_cntrl_reg(struct intel_display display) in intel_vga_cntrl_reg() argument 19 if (display->platform.valleyview \|\| display->platform.cherryview) in intel_vga_cntrl_reg() 21 else if (DISPLAY_VER(display) >= 5) in intel_vga_cntrl_reg() 28 void intel_vga_disable(struct intel_display display) in intel_vga_disable() argument 30 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in intel_vga_disable() 31 i915_reg_t vga_reg = intel_vga_cntrl_reg(display); in intel_vga_disable() 34 if (intel_de_read(display, vga_reg) & VGA_DISP_DISABLE) in intel_vga_disable() 45 intel_de_write(display, vga_reg, VGA_DISP_DISABLE); in intel_vga_disable() 46 intel_de_posting_read(display, vga_reg); in intel_vga_disable() [all …]
D	intel_dmc_wl.c	1 // SPDX-License-Identifier: MIT 19 * Wake lock is the mechanism to cause display engine to exit DC 29 * The wakelock mechanism in DMC allows the display engine to exit DC 32 * implicitly when the display engine accessed a register. With the 33 * wakelock implementation, the driver asserts a wakelock in DMC, 53 * Possible non-negative values for the enable_dmc_wl param. 156 static void __intel_dmc_wl_release(struct intel_display display) in __intel_dmc_wl_release() argument 158 struct drm_i915_private i915 = to_i915(display->drm); in __intel_dmc_wl_release() 159 struct intel_dmc_wl *wl = &display->wl; in __intel_dmc_wl_release() 161 WARN_ON(refcount_read(&wl->refcount)); in __intel_dmc_wl_release() [all …]
D	intel_hotplug.c	4 * Permission is hereby granted, free of charge, to any person obtaining a 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 41 * Simply put, hotplug occurs when a display is connected to or disconnected 43 * Display Port short pulses and MST devices involved, complicating matters. 50 * into a platform independent mask of hotplug pins that have fired. 54 * further processing to appropriate bottom halves (Display Port specific and 57 * The Display Port work function i915_digport_work_func() calls into 59 * pulses, with failures and non-MST long pulses triggering regular hotplug 66 * Finally, the userspace is responsible for triggering a modeset upon receiving 70 * number of interrupts per hotplug pin per a period of time, and if the number [all …]
/linux-6.15/drivers/media/platform/renesas/vsp1/
D	vsp1_dl.c	1 // SPDX-License-Identifier: GPL-2.0+ 3 * vsp1_dl.c -- R-Car VSP1 Display List 11 #include <linux/dma-mapping.h> 41 * struct vsp1_dl_ext_header - Extended display list header 43 * @pre_ext_dl_num_cmd: number of pre-extended command bodies to parse 45 * @pre_ext_dl_plist: start address of pre-extended display list bodies 46 * @post_ext_dl_num_cmd: number of post-extended command bodies to parse 47 * @post_ext_dl_plist: start address of post-extended display list bodies 54 * expecting 32-bit accesses. The flags are appropriate to the whole 79 * struct vsp1_pre_ext_dl_body - Pre Extended Display List Body [all …]
/linux-6.15/Documentation/gpu/amdgpu/display/
D	dc-debug.rst	2 Display Core Debug tools 6 driver from the display perspective. This page introduces debug mechanisms and 7 procedures to help you identify if some issues are related to display code. 9 Narrow down display issues 12 Since the display is the driver's visual component, it is common to see users 13 reporting issues as a display when another component causes the problem. This 14 section equips users to determine if a specific issue was caused by the display 18 --------------------------- 43 (Display Manager), was loaded, which means that display can be part of the 45 amdgpu loads the display component, indicating that we don't have a [all …]
/linux-6.15/drivers/gpu/drm/xe/display/
D	xe_display.c	1 // SPDX-License-Identifier: MIT 41 return HAS_DISPLAY(&xe->display); in has_display() 45 * xe_display_driver_probe_defer - Detect if we need to wait for other drivers 60 * xe_display_driver_set_hooks - Add driver flags and hooks for display 64 * display IP. This sets the driver's capability of driving display, regardless 73 driver->fbdev_probe = intel_fbdev_driver_fbdev_probe; in xe_display_driver_set_hooks() 76 driver->driver_features \|= DRIVER_MODESET \| DRIVER_ATOMIC; in xe_display_driver_set_hooks() 81 xe->drm.driver_features &= ~(DRIVER_MODESET \| DRIVER_ATOMIC); in unset_display_features() 88 destroy_workqueue(xe->display.hotplug.dp_wq); in display_destroy() 92 * xe_display_create - create display struct [all …]

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