1 // SPDX-License-Identifier: MIT
18 	struct intel_display *display = to_intel_display(crtc_state);  in hsw_ips_enable()  local
19 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_ips_enable()
20 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_ips_enable()
23 	if (!crtc_state->ips_enabled)  in hsw_ips_enable()
27 	 * We can only enable IPS after we enable a plane and wait for a vblank  in hsw_ips_enable()
29 	 * a vblank wait.  in hsw_ips_enable()
31 	drm_WARN_ON(display->drm,  in hsw_ips_enable()
32 		    !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));  in hsw_ips_enable()
36 	if (display->ips.false_color)  in hsw_ips_enable()
39 	if (display->platform.broadwell) {  in hsw_ips_enable()
40 		drm_WARN_ON(display->drm,  in hsw_ips_enable()
41 			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,  in hsw_ips_enable()
46 		 * mailbox." Moreover, the mailbox may return a bogus state,  in hsw_ips_enable()
50 		intel_de_write(display, IPS_CTL, val);  in hsw_ips_enable()
58 		if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))  in hsw_ips_enable()
59 			drm_err(display->drm,  in hsw_ips_enable()
66 	struct intel_display *display = to_intel_display(crtc_state);  in hsw_ips_disable()  local
67 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_ips_disable()
68 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_ips_disable()
71 	if (!crtc_state->ips_enabled)  in hsw_ips_disable()
74 	if (display->platform.broadwell) {  in hsw_ips_disable()
75 		drm_WARN_ON(display->drm,  in hsw_ips_disable()
76 			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));  in hsw_ips_disable()
82 		if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE, 100))  in hsw_ips_disable()
83 			drm_err(display->drm,  in hsw_ips_disable()
86 		intel_de_write(display, IPS_CTL, 0);  in hsw_ips_disable()
87 		intel_de_posting_read(display, IPS_CTL);  in hsw_ips_disable()
90 	/* We need to wait for a vblank before we can disable the plane. */  in hsw_ips_disable()
99 	struct intel_display *display = to_intel_display(state);  in hsw_ips_need_disable()  local
105 	if (!old_crtc_state->ips_enabled)  in hsw_ips_need_disable()
117 	if (display->platform.haswell &&  in hsw_ips_need_disable()
119 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)  in hsw_ips_need_disable()
122 	return !new_crtc_state->ips_enabled;  in hsw_ips_need_disable()
140 	struct intel_display *display = to_intel_display(state);  in hsw_ips_need_enable()  local
146 	if (!new_crtc_state->ips_enabled)  in hsw_ips_need_enable()
156 	 * Re-enable IPS after the LUT has been programmed.  in hsw_ips_need_enable()
158 	if (display->platform.haswell &&  in hsw_ips_need_enable()
160 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)  in hsw_ips_need_enable()
167 	if (intel_crtc_needs_fastset(new_crtc_state) && old_crtc_state->inherited)  in hsw_ips_need_enable()
170 	return !old_crtc_state->ips_enabled;  in hsw_ips_need_enable()
185 /* IPS only exists on ULT machines and is tied to pipe A. */
188 	struct intel_display *display = to_intel_display(crtc);  in hsw_crtc_supports_ips()  local
190 	return HAS_IPS(display) && crtc->pipe == PIPE_A;  in hsw_crtc_supports_ips()
195 	struct intel_display *display = to_intel_display(crtc_state);  in hsw_crtc_state_ips_capable()  local
196 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_crtc_state_ips_capable()
198 	/* IPS only exists on ULT machines and is tied to pipe A. */  in hsw_crtc_state_ips_capable()
202 	if (!display->params.enable_ips)  in hsw_crtc_state_ips_capable()
205 	if (crtc_state->pipe_bpp > 24)  in hsw_crtc_state_ips_capable()
213 	 * Should measure whether using a lower cdclk w/o IPS  in hsw_crtc_state_ips_capable()
215 	if (display->platform.broadwell &&  in hsw_crtc_state_ips_capable()
216 	    crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)  in hsw_crtc_state_ips_capable()
224 	struct intel_display *display = to_intel_display(crtc_state);  in hsw_ips_min_cdclk()  local
226 	if (!display->platform.broadwell)  in hsw_ips_min_cdclk()
233 	return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);  in hsw_ips_min_cdclk()
239 	struct intel_display *display = to_intel_display(state);  in hsw_ips_compute_config()  local
243 	crtc_state->ips_enabled = false;  in hsw_ips_compute_config()
254 	if (crtc_state->crc_enabled)  in hsw_ips_compute_config()
258 	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))  in hsw_ips_compute_config()
261 	if (display->platform.broadwell) {  in hsw_ips_compute_config()
269 		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)  in hsw_ips_compute_config()
273 	crtc_state->ips_enabled = true;  in hsw_ips_compute_config()
280 	struct intel_display *display = to_intel_display(crtc_state);  in hsw_ips_get_config()  local
281 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_ips_get_config()
286 	if (display->platform.haswell) {  in hsw_ips_get_config()
287 		crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;  in hsw_ips_get_config()
291 		 * true so we can set it to a defined state on first  in hsw_ips_get_config()
294 		crtc_state->ips_enabled = true;  in hsw_ips_get_config()
301 	struct intel_display *display = to_intel_display(crtc);  in hsw_ips_debugfs_false_color_get()  local
303 	*val = display->ips.false_color;  in hsw_ips_debugfs_false_color_get()
311 	struct intel_display *display = to_intel_display(crtc);  in hsw_ips_debugfs_false_color_set()  local
315 	ret = drm_modeset_lock(&crtc->base.mutex, NULL);  in hsw_ips_debugfs_false_color_set()
319 	display->ips.false_color = val;  in hsw_ips_debugfs_false_color_set()
321 	crtc_state = to_intel_crtc_state(crtc->base.state);  in hsw_ips_debugfs_false_color_set()
323 	if (!crtc_state->hw.active)  in hsw_ips_debugfs_false_color_set()
326 	if (crtc_state->uapi.commit &&  in hsw_ips_debugfs_false_color_set()
327 	    !try_wait_for_completion(&crtc_state->uapi.commit->hw_done))  in hsw_ips_debugfs_false_color_set()
333 	drm_modeset_unlock(&crtc->base.mutex);  in hsw_ips_debugfs_false_color_set()
345 	struct intel_crtc *crtc = m->private;  in hsw_ips_debugfs_status_show()
346 	struct intel_display *display = to_intel_display(crtc);  in hsw_ips_debugfs_status_show()  local
347 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_ips_debugfs_status_show()
350 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);  in hsw_ips_debugfs_status_show()
353 		   str_yes_no(display->params.enable_ips));  in hsw_ips_debugfs_status_show()
355 	if (DISPLAY_VER(display) >= 8) {  in hsw_ips_debugfs_status_show()
358 		if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)  in hsw_ips_debugfs_status_show()
364 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);  in hsw_ips_debugfs_status_show()
376 	debugfs_create_file("i915_ips_false_color", 0644, crtc->base.debugfs_entry,  in hsw_ips_crtc_debugfs_add()
379 	debugfs_create_file("i915_ips_status", 0444, crtc->base.debugfs_entry,  in hsw_ips_crtc_debugfs_add()