Lines Matching +full:a +full:- +full:display
2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
91 bool intel_crt_port_enabled(struct intel_display *display, in intel_crt_port_enabled() argument
94 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_crt_port_enabled()
97 val = intel_de_read(display, adpa_reg); in intel_crt_port_enabled()
111 struct intel_display *display = to_intel_display(encoder); in intel_crt_get_hw_state() local
116 wakeref = intel_display_power_get_if_enabled(display, in intel_crt_get_hw_state()
117 encoder->power_domain); in intel_crt_get_hw_state()
121 ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); in intel_crt_get_hw_state()
123 intel_display_power_put(display, encoder->power_domain, wakeref); in intel_crt_get_hw_state()
130 struct intel_display *display = to_intel_display(encoder); in intel_crt_get_flags() local
134 tmp = intel_de_read(display, crt->adpa_reg); in intel_crt_get_flags()
152 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_crt_get_config()
154 crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
156 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_crt_get_config()
166 crtc_state->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
170 crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
179 struct intel_display *display = to_intel_display(encoder); in intel_crt_set_dpms() local
180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_crt_set_dpms()
182 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crt_set_dpms()
183 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_crt_set_dpms()
186 if (DISPLAY_VER(display) >= 5) in intel_crt_set_dpms()
191 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) in intel_crt_set_dpms()
193 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) in intel_crt_set_dpms()
196 /* For CPT allow 3 pipe config, for others just use A or B */ in intel_crt_set_dpms()
200 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); in intel_crt_set_dpms()
202 adpa |= ADPA_PIPE_SEL(crtc->pipe); in intel_crt_set_dpms()
205 intel_de_write(display, BCLRPAT(display, crtc->pipe), 0); in intel_crt_set_dpms()
222 intel_de_write(display, crt->adpa_reg, adpa); in intel_crt_set_dpms()
253 struct intel_display *display = to_intel_display(encoder); in hsw_disable_crt() local
255 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); in hsw_disable_crt()
257 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in hsw_disable_crt()
265 struct intel_display *display = to_intel_display(encoder); in hsw_post_disable_crt() local
266 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in hsw_post_disable_crt()
284 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); in hsw_post_disable_crt()
286 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in hsw_post_disable_crt()
294 struct intel_display *display = to_intel_display(encoder); in hsw_pre_pll_enable_crt() local
296 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); in hsw_pre_pll_enable_crt()
298 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in hsw_pre_pll_enable_crt()
306 struct intel_display *display = to_intel_display(encoder); in hsw_pre_enable_crt() local
307 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_pre_enable_crt()
308 enum pipe pipe = crtc->pipe; in hsw_pre_enable_crt()
310 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); in hsw_pre_enable_crt()
312 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); in hsw_pre_enable_crt()
324 struct intel_display *display = to_intel_display(encoder); in hsw_enable_crt() local
325 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_enable_crt()
326 enum pipe pipe = crtc->pipe; in hsw_enable_crt()
328 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); in hsw_enable_crt()
342 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); in hsw_enable_crt()
343 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in hsw_enable_crt()
358 struct intel_display *display = to_intel_display(connector->dev); in intel_crt_mode_valid() local
359 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_crt_mode_valid()
360 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_crt_mode_valid()
364 status = intel_cpu_transcoder_mode_valid(display, mode); in intel_crt_mode_valid()
368 if (mode->clock < 25000) in intel_crt_mode_valid()
379 else if (IS_DISPLAY_VER(display, 3, 4)) in intel_crt_mode_valid()
383 if (mode->clock > max_clock) in intel_crt_mode_valid()
386 if (mode->clock > max_dotclk) in intel_crt_mode_valid()
391 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) in intel_crt_mode_valid()
395 if (mode->hdisplay > 4096) in intel_crt_mode_valid()
406 &crtc_state->hw.adjusted_mode; in intel_crt_compute_config()
408 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_crt_compute_config()
409 return -EINVAL; in intel_crt_compute_config()
411 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_crt_compute_config()
412 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_crt_compute_config()
422 &crtc_state->hw.adjusted_mode; in pch_crt_compute_config()
424 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in pch_crt_compute_config()
425 return -EINVAL; in pch_crt_compute_config()
427 crtc_state->has_pch_encoder = true; in pch_crt_compute_config()
429 return -EINVAL; in pch_crt_compute_config()
431 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; in pch_crt_compute_config()
440 struct intel_display *display = to_intel_display(encoder); in hsw_crt_compute_config() local
441 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_crt_compute_config()
443 &crtc_state->hw.adjusted_mode; in hsw_crt_compute_config()
445 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in hsw_crt_compute_config()
446 return -EINVAL; in hsw_crt_compute_config()
449 if (adjusted_mode->crtc_hdisplay > 4096 || in hsw_crt_compute_config()
450 adjusted_mode->crtc_hblank_start > 4096) in hsw_crt_compute_config()
451 return -EINVAL; in hsw_crt_compute_config()
453 crtc_state->has_pch_encoder = true; in hsw_crt_compute_config()
455 return -EINVAL; in hsw_crt_compute_config()
457 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; in hsw_crt_compute_config()
461 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ in hsw_crt_compute_config()
462 if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) { in hsw_crt_compute_config()
463 drm_dbg_kms(display->drm, in hsw_crt_compute_config()
465 return -EINVAL; in hsw_crt_compute_config()
468 crtc_state->pipe_bpp = 24; in hsw_crt_compute_config()
472 crtc_state->port_clock = 135000 * 2; in hsw_crt_compute_config()
474 crtc_state->enhanced_framing = true; in hsw_crt_compute_config()
476 adjusted_mode->crtc_clock = lpt_iclkip(crtc_state); in hsw_crt_compute_config()
483 struct intel_display *display = to_intel_display(connector->dev); in ilk_crt_detect_hotplug() local
485 struct drm_i915_private *dev_priv = to_i915(connector->dev); in ilk_crt_detect_hotplug()
490 if (crt->force_hotplug_required) { in ilk_crt_detect_hotplug()
494 crt->force_hotplug_required = false; in ilk_crt_detect_hotplug()
496 save_adpa = adpa = intel_de_read(display, crt->adpa_reg); in ilk_crt_detect_hotplug()
497 drm_dbg_kms(display->drm, in ilk_crt_detect_hotplug()
504 intel_de_write(display, crt->adpa_reg, adpa); in ilk_crt_detect_hotplug()
506 if (intel_de_wait_for_clear(display, in ilk_crt_detect_hotplug()
507 crt->adpa_reg, in ilk_crt_detect_hotplug()
510 drm_dbg_kms(display->drm, in ilk_crt_detect_hotplug()
514 intel_de_write(display, crt->adpa_reg, save_adpa); in ilk_crt_detect_hotplug()
515 intel_de_posting_read(display, crt->adpa_reg); in ilk_crt_detect_hotplug()
520 adpa = intel_de_read(display, crt->adpa_reg); in ilk_crt_detect_hotplug()
525 drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n", in ilk_crt_detect_hotplug()
533 struct intel_display *display = to_intel_display(connector->dev); in valleyview_crt_detect_hotplug() local
535 struct drm_i915_private *dev_priv = to_i915(connector->dev); in valleyview_crt_detect_hotplug()
542 * Doing a force trigger causes a hpd interrupt to get sent, which can in valleyview_crt_detect_hotplug()
543 * get us stuck in a loop if we're polling: in valleyview_crt_detect_hotplug()
544 * - We enable power wells and reset the ADPA in valleyview_crt_detect_hotplug()
545 * - output_poll_exec does force probe on VGA, triggering a hpd in valleyview_crt_detect_hotplug()
546 * - HPD handler waits for poll to unlock dev->mode_config.mutex in valleyview_crt_detect_hotplug()
547 * - output_poll_exec shuts off the ADPA, unlocks in valleyview_crt_detect_hotplug()
548 * dev->mode_config.mutex in valleyview_crt_detect_hotplug()
549 * - HPD handler runs, resets ADPA and brings us back to the start in valleyview_crt_detect_hotplug()
553 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); in valleyview_crt_detect_hotplug()
555 save_adpa = adpa = intel_de_read(display, crt->adpa_reg); in valleyview_crt_detect_hotplug()
556 drm_dbg_kms(display->drm, in valleyview_crt_detect_hotplug()
561 intel_de_write(display, crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
563 if (intel_de_wait_for_clear(display, crt->adpa_reg, in valleyview_crt_detect_hotplug()
565 drm_dbg_kms(display->drm, in valleyview_crt_detect_hotplug()
567 intel_de_write(display, crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
571 adpa = intel_de_read(display, crt->adpa_reg); in valleyview_crt_detect_hotplug()
577 drm_dbg_kms(display->drm, in valleyview_crt_detect_hotplug()
581 intel_hpd_enable(dev_priv, crt->base.hpd_pin); in valleyview_crt_detect_hotplug()
588 struct intel_display *display = to_intel_display(connector->dev); in intel_crt_detect_hotplug() local
589 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_crt_detect_hotplug()
602 * to get a reliable result. in intel_crt_detect_hotplug()
616 if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display), in intel_crt_detect_hotplug()
618 drm_dbg_kms(display->drm, in intel_crt_detect_hotplug()
622 stat = intel_de_read(display, PORT_HOTPLUG_STAT(display)); in intel_crt_detect_hotplug()
627 intel_de_write(display, PORT_HOTPLUG_STAT(display), in intel_crt_detect_hotplug()
643 drm_dbg_kms(connector->dev, in intel_crt_get_edid()
644 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); in intel_crt_get_edid()
673 struct intel_display *display = to_intel_display(connector->dev); in intel_crt_detect_ddc() local
677 drm_edid = intel_crt_get_edid(connector, connector->ddc); in intel_crt_detect_ddc()
681 * This may be a DVI-I connector with a shared DDC in intel_crt_detect_ddc()
686 drm_dbg_kms(display->drm, in intel_crt_detect_ddc()
687 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); in intel_crt_detect_ddc()
689 drm_dbg_kms(display->drm, in intel_crt_detect_ddc()
694 drm_dbg_kms(display->drm, in intel_crt_detect_ddc()
706 struct intel_display *display = to_intel_display(&crt->base); in intel_crt_load_detect() local
717 drm_dbg_kms(display->drm, "starting load-detect on CRT\n"); in intel_crt_load_detect()
719 save_bclrpat = intel_de_read(display, in intel_crt_load_detect()
720 BCLRPAT(display, cpu_transcoder)); in intel_crt_load_detect()
721 save_vtotal = intel_de_read(display, in intel_crt_load_detect()
722 TRANS_VTOTAL(display, cpu_transcoder)); in intel_crt_load_detect()
723 vblank = intel_de_read(display, in intel_crt_load_detect()
724 TRANS_VBLANK(display, cpu_transcoder)); in intel_crt_load_detect()
733 intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050); in intel_crt_load_detect()
735 if (DISPLAY_VER(display) != 2) { in intel_crt_load_detect()
736 u32 transconf = intel_de_read(display, in intel_crt_load_detect()
737 TRANSCONF(display, cpu_transcoder)); in intel_crt_load_detect()
739 intel_de_write(display, TRANSCONF(display, cpu_transcoder), in intel_crt_load_detect()
741 intel_de_posting_read(display, in intel_crt_load_detect()
742 TRANSCONF(display, cpu_transcoder)); in intel_crt_load_detect()
747 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); in intel_crt_load_detect()
748 st00 = intel_de_read8(display, _VGA_MSR_WRITE); in intel_crt_load_detect()
753 intel_de_write(display, TRANSCONF(display, cpu_transcoder), in intel_crt_load_detect()
764 u32 vsync = intel_de_read(display, in intel_crt_load_detect()
765 TRANS_VSYNC(display, cpu_transcoder)); in intel_crt_load_detect()
769 intel_de_write(display, in intel_crt_load_detect()
770 TRANS_VBLANK(display, cpu_transcoder), in intel_crt_load_detect()
771 VBLANK_START(vblank_start - 1) | in intel_crt_load_detect()
772 VBLANK_END(vblank_end - 1)); in intel_crt_load_detect()
776 if (vblank_start - vactive >= vtotal - vblank_end) in intel_crt_load_detect()
784 while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive) in intel_crt_load_detect()
786 while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample) in intel_crt_load_detect()
796 st00 = intel_de_read8(display, _VGA_MSR_WRITE); in intel_crt_load_detect()
799 } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl)); in intel_crt_load_detect()
803 intel_de_write(display, in intel_crt_load_detect()
804 TRANS_VBLANK(display, cpu_transcoder), in intel_crt_load_detect()
807 * If more than 3/4 of the scanline detected a monitor, in intel_crt_load_detect()
818 intel_de_write(display, BCLRPAT(display, cpu_transcoder), in intel_crt_load_detect()
826 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); in intel_spurious_crt_detect_dmi_callback()
841 .ident = "Intel DZ77BH-55K",
844 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
855 struct intel_display *display = to_intel_display(connector->dev); in intel_crt_detect() local
857 struct intel_encoder *encoder = &crt->base; in intel_crt_detect()
862 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n", in intel_crt_detect()
863 connector->base.id, connector->name, in intel_crt_detect()
866 if (!intel_display_device_enabled(display)) in intel_crt_detect()
869 if (!intel_display_driver_check_access(display)) in intel_crt_detect()
870 return connector->status; in intel_crt_detect()
872 if (display->params.load_detect_test) { in intel_crt_detect()
873 wakeref = intel_display_power_get(display, encoder->power_domain); in intel_crt_detect()
881 wakeref = intel_display_power_get(display, encoder->power_domain); in intel_crt_detect()
883 if (I915_HAS_HOTPLUG(display)) { in intel_crt_detect()
889 drm_dbg_kms(display->drm, in intel_crt_detect()
894 drm_dbg_kms(display->drm, in intel_crt_detect()
903 /* Load detection is broken on HPD capable machines. Whoever wants a in intel_crt_detect()
904 * broken monitor (without edid) to work behind a broken kvm (that fails in intel_crt_detect()
907 if (I915_HAS_HOTPLUG(display)) { in intel_crt_detect()
914 status = connector->status; in intel_crt_detect()
918 /* for pre-945g platforms use load detect */ in intel_crt_detect()
927 else if (DISPLAY_VER(display) < 4) in intel_crt_detect()
929 to_intel_crtc(connector->state->crtc)->pipe); in intel_crt_detect()
930 else if (display->params.load_detect_test) in intel_crt_detect()
938 intel_display_power_put(display, encoder->power_domain, wakeref); in intel_crt_detect()
945 struct intel_display *display = to_intel_display(connector->dev); in intel_crt_get_modes() local
946 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_crt_get_modes()
948 struct intel_encoder *encoder = &crt->base; in intel_crt_get_modes()
953 if (!intel_display_driver_check_access(display)) in intel_crt_get_modes()
956 wakeref = intel_display_power_get(display, encoder->power_domain); in intel_crt_get_modes()
958 ret = intel_crt_ddc_get_modes(connector, connector->ddc); in intel_crt_get_modes()
962 /* Try to probe digital port for output in DVI-I -> VGA mode. */ in intel_crt_get_modes()
963 ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB); in intel_crt_get_modes()
967 intel_display_power_put(display, encoder->power_domain, wakeref); in intel_crt_get_modes()
974 struct intel_display *display = to_intel_display(encoder->dev); in intel_crt_reset() local
977 if (DISPLAY_VER(display) >= 5) { in intel_crt_reset()
980 adpa = intel_de_read(display, crt->adpa_reg); in intel_crt_reset()
983 intel_de_write(display, crt->adpa_reg, adpa); in intel_crt_reset()
984 intel_de_posting_read(display, crt->adpa_reg); in intel_crt_reset()
986 drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa); in intel_crt_reset()
987 crt->force_hotplug_required = true; in intel_crt_reset()
1016 void intel_crt_init(struct intel_display *display) in intel_crt_init() argument
1018 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_crt_init()
1032 adpa = intel_de_read(display, adpa_reg); in intel_crt_init()
1042 intel_de_write(display, adpa_reg, in intel_crt_init()
1046 if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0) in intel_crt_init()
1048 intel_de_write(display, adpa_reg, adpa); in intel_crt_init()
1061 ddc_pin = display->vbt.crt_ddc_pin; in intel_crt_init()
1063 drm_connector_init_with_ddc(display->drm, &connector->base, in intel_crt_init()
1066 intel_gmbus_get_adapter(display, ddc_pin)); in intel_crt_init()
1068 drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs, in intel_crt_init()
1071 intel_connector_attach_encoder(connector, &crt->base); in intel_crt_init()
1073 crt->base.type = INTEL_OUTPUT_ANALOG; in intel_crt_init()
1074 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); in intel_crt_init()
1076 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1078 crt->base.pipe_mask = ~0; in intel_crt_init()
1080 if (DISPLAY_VER(display) != 2) in intel_crt_init()
1081 connector->base.interlace_allowed = true; in intel_crt_init()
1083 crt->adpa_reg = adpa_reg; in intel_crt_init()
1085 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; in intel_crt_init()
1087 if (I915_HAS_HOTPLUG(display) && in intel_crt_init()
1089 crt->base.hpd_pin = HPD_CRT; in intel_crt_init()
1090 crt->base.hotplug = intel_encoder_hotplug; in intel_crt_init()
1091 connector->polled = DRM_CONNECTOR_POLL_HPD; in intel_crt_init()
1093 connector->polled = DRM_CONNECTOR_POLL_CONNECT; in intel_crt_init()
1095 connector->base.polled = connector->polled; in intel_crt_init()
1097 if (HAS_DDI(display)) { in intel_crt_init()
1098 assert_port_valid(display, PORT_E); in intel_crt_init()
1100 crt->base.port = PORT_E; in intel_crt_init()
1101 crt->base.get_config = hsw_crt_get_config; in intel_crt_init()
1102 crt->base.get_hw_state = intel_ddi_get_hw_state; in intel_crt_init()
1103 crt->base.compute_config = hsw_crt_compute_config; in intel_crt_init()
1104 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; in intel_crt_init()
1105 crt->base.pre_enable = hsw_pre_enable_crt; in intel_crt_init()
1106 crt->base.enable = hsw_enable_crt; in intel_crt_init()
1107 crt->base.disable = hsw_disable_crt; in intel_crt_init()
1108 crt->base.post_disable = hsw_post_disable_crt; in intel_crt_init()
1109 crt->base.enable_clock = hsw_ddi_enable_clock; in intel_crt_init()
1110 crt->base.disable_clock = hsw_ddi_disable_clock; in intel_crt_init()
1111 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; in intel_crt_init()
1113 intel_ddi_buf_trans_init(&crt->base); in intel_crt_init()
1116 crt->base.compute_config = pch_crt_compute_config; in intel_crt_init()
1117 crt->base.disable = pch_disable_crt; in intel_crt_init()
1118 crt->base.post_disable = pch_post_disable_crt; in intel_crt_init()
1120 crt->base.compute_config = intel_crt_compute_config; in intel_crt_init()
1121 crt->base.disable = intel_disable_crt; in intel_crt_init()
1123 crt->base.port = PORT_NONE; in intel_crt_init()
1124 crt->base.get_config = intel_crt_get_config; in intel_crt_init()
1125 crt->base.get_hw_state = intel_crt_get_hw_state; in intel_crt_init()
1126 crt->base.enable = intel_enable_crt; in intel_crt_init()
1128 connector->get_hw_state = intel_connector_get_hw_state; in intel_crt_init()
1130 drm_connector_helper_add(&connector->base, &intel_crt_connector_helper_funcs); in intel_crt_init()
1133 * TODO: find a proper way to discover whether we need to set the the in intel_crt_init()
1141 display->fdi.rx_config = intel_de_read(display, in intel_crt_init()
1145 intel_crt_reset(&crt->base.base); in intel_crt_init()