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/qemu/hw/char/
H A Dgrlib_apbuart.c2 * QEMU GRLIB APB UART Emulator
41 /* UART status register fields */
54 /* UART control register fields */
79 OBJECT_DECLARE_SIMPLE_TYPE(UART, GRLIB_APB_UART)
81 struct UART { struct
99 static int uart_data_to_read(UART *uart) in uart_data_to_read() argument
101 return uart->current < uart->len; in uart_data_to_read()
104 static char uart_pop(UART *uart) in uart_pop() argument
108 if (uart->len == 0) { in uart_pop()
109 uart->status &= ~UART_DATA_READY; in uart_pop()
[all …]
H A Dtrace-events71 # cmsdk-apb-uart.c
72 cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART read: offset 0x%…
73 cmsdk_apb_uart_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART write: offset 0…
74 cmsdk_apb_uart_reset(void) "CMSDK APB UART: reset"
75 cmsdk_apb_uart_receive(uint8_t c) "CMSDK APB UART: got character 0x%x from backend"
76 cmsdk_apb_uart_tx_pending(void) "CMSDK APB UART: character send to backend pending"
77 cmsdk_apb_uart_tx(uint8_t c) "CMSDK APB UART: character 0x%x sent to backend"
78 cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
89 exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
90 exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
[all …]
H A Dcmsdk-apb-uart.c2 * ARM CMSDK APB UART emulation
12 /* This is a model of the "APB UART" which is part of the Cortex-M
28 #include "hw/char/cmsdk-apb-uart.h"
85 /* This UART is always 8N1 but the baud rate is programmable. */ in uart_update_parameters()
183 "CMSDK APB UART read: bad offset %x\n", (int) offset); in uart_read()
272 "CMSDK APB UART: Tx enabled with invalid baudrate\n"); in uart_write()
291 "CMSDK APB UART write: write to RO offset 0x%x\n", in uart_write()
296 "CMSDK APB UART write: bad offset 0x%x\n", (int) offset); in uart_write()
326 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); in cmsdk_apb_uart_init()
340 error_setg(errp, "CMSDK APB UART: pclk-frq property must be set"); in cmsdk_apb_uart_realize()
[all …]
H A Ddigic-uart.c2 * QEMU model of the Canon DIGIC UART block.
14 * The QEMU model of the Milkymist UART block by Michael Walle
36 #include "hw/char/digic-uart.h"
65 "digic-uart: read access to unknown register 0x" in digic_uart_read()
103 "digic-uart: write access to unknown register 0x" in digic_uart_write()
165 .name = "digic-uart",
H A Dexynos4210_uart.c2 * Exynos4210 UART Emulation
41 * Offsets for UART registers relative to SFR base address
50 #define UERSTAT 0x0014 /* UART Error Status */
95 /* UART FIFO Control */
104 /* Uart FIFO Status */
113 /* UART Interrupt Source Pending */
119 /* UART Line Control */
124 /* UART Tx/Rx Status */
130 /* UART Error Status */
142 #define TYPE_EXYNOS4210_UART "exynos4210.uart"
[all …]
H A Dbcm2835_aux.c2 * BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI).
7 * Arm PrimeCell PL011 UART
14 * At present only the core UART functions (data path for tx/rx) are
76 return 1; /* mini UART permanently enabled */ in bcm2835_aux_read()
167 " or disable UART: 0x%"PRIx64"\n", in bcm2835_aux_write()
/qemu/docs/system/arm/
H A Dmps2.rst70 Note that for the AN536 the first UART is accessible only by
71 CPU0, and the second UART is accessible only by CPU1. The
72 first UART accessible shared between both CPUs is the third
73 UART. Guest software might therefore be built to use either
74 the first UART or the third UART; if you don't see any output
75 from the UART you are looking at, try one of the others.
77 no "CPU1-only UART", the UART numbering remains the same,
78 with the third UART being the first of the shared ones.)
/qemu/hw/arm/
H A DKconfig24 select PL011 # UART
77 select PL011 # UART
90 select PL011 # UART
108 select PL011 # UART
171 select PL011 # UART
196 select PL011 # UART
220 select PL011 # UART
280 select PL011 # UART
292 select CADENCE # UART
299 select XILINX # UART
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H A Daspeed_soc_common.c39 for (int i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) { in aspeed_soc_uart_realize() local
40 smm = &s->uart[i]; in aspeed_soc_uart_realize()
45 qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); in aspeed_soc_uart_realize()
51 sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart)); in aspeed_soc_uart_realize()
52 aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); in aspeed_soc_uart_realize()
65 g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); in aspeed_soc_uart_set_chr()
66 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); in aspeed_soc_uart_set_chr()
H A Ddigic.c46 object_initialize_child(obj, "uart", &s->uart, TYPE_DIGIC_UART); in digic_init()
73 qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0)); in digic_realize()
74 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { in digic_realize()
78 sbd = SYS_BUS_DEVICE(&s->uart); in digic_realize()
H A Dnrf51_soc.c100 /* UART */ in nrf51_soc_realize()
101 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { in nrf51_soc_realize()
104 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); in nrf51_soc_realize()
106 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, in nrf51_soc_realize()
193 object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART); in nrf51_soc_init()
194 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev"); in nrf51_soc_init()
H A Dmps2-tz.c61 #include "hw/char/cmsdk-apb-uart.h"
125 int uart_overflow_irq; /* number of the combined UART overflow IRQ */
158 CMSDKAPBUART uart[6]; member
440 CMSDKAPBUART *uart = opaque; in make_uart() local
441 int i = uart - &mms->uart[0]; in make_uart()
445 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); in make_uart()
446 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); in make_uart()
447 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); in make_uart()
448 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); in make_uart()
449 s = SYS_BUS_DEVICE(uart); in make_uart()
[all …]
H A Dmps3r.c40 #include "hw/char/cmsdk-apb-uart.h"
81 #define MPS3R_UART_MAX 4 /* shared UART count */
107 CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX]; member
327 * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
328 * The qemu_irq arguments are where we connect the various IRQs from the UART.
335 g_autofree char *s = g_strdup_printf("uart%d", uartno); in create_uart()
338 assert(uartno < ARRAY_SIZE(mms->uart)); in create_uart()
339 object_initialize_child(OBJECT(mms), s, &mms->uart[uartno], in create_uart()
341 qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ); in create_uart()
342 qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno)); in create_uart()
[all …]
H A Dmusca.c76 PL011State uart[2]; member
290 PL011State *uart = opaque; in make_uart() local
291 int i = uart - &mms->uart[0]; in make_uart()
295 object_initialize_child(OBJECT(mms), name, uart, TYPE_PL011); in make_uart()
296 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); in make_uart()
297 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); in make_uart()
298 s = SYS_BUS_DEVICE(uart); in make_uart()
305 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); in make_uart()
323 { "uart0", make_uart, &mms->uart[0], 0x1000, 0x1000 }, in make_musca_a_devs()
324 { "uart1", make_uart, &mms->uart[1], 0x2000, 0x1000 }, in make_musca_a_devs()
[all …]
H A Dfsl-imx31.c43 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL); in fsl_imx31_init()
96 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); in fsl_imx31_realize()
98 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { in fsl_imx31_realize()
102 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); in fsl_imx31_realize()
103 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, in fsl_imx31_realize()
H A Dfsl-imx25.c47 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL); in fsl_imx25_init()
117 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); in fsl_imx25_realize()
119 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { in fsl_imx25_realize()
122 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); in fsl_imx25_realize()
123 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, in fsl_imx25_realize()
/qemu/include/hw/char/
H A Dcmsdk-apb-uart.h2 * ARM CMSDK APB UART emulation
19 #define TYPE_CMSDK_APB_UART "cmsdk-apb-uart"
41 /* This UART has no FIFO, only a 1-character buffer for each of Tx and Rx */
H A Ddigic-uart.h2 * Canon DIGIC UART block declarations.
25 #define TYPE_DIGIC_UART "digic-uart"
/qemu/hw/riscv/
H A Dopentitan.c135 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); in lowrisc_ibex_soc_init()
203 /* UART */ in lowrisc_ibex_soc_realize()
204 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0)); in lowrisc_ibex_soc_realize()
205 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { in lowrisc_ibex_soc_realize()
208 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); in lowrisc_ibex_soc_realize()
209 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), in lowrisc_ibex_soc_realize()
212 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), in lowrisc_ibex_soc_realize()
215 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), in lowrisc_ibex_soc_realize()
218 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), in lowrisc_ibex_soc_realize()
H A Dshakti_c.c131 qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); in type_init()
132 if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { in type_init()
135 sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0, in type_init()
163 object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART); in shakti_c_soc_instance_init()
/qemu/rust/hw/char/pl011/src/
H A Dregisters.rs51 /// Toggle UART, transmission or reception
161 /// BUSY: UART busy. In real hardware, set while the UART is
282 /// `UARTEN` UART enable: 0 = UART is disabled.
291 /// `LBE` Loopback enable: feed UART output back to the input
301 /// `Out1` UART Out1 signal; can be used as DCD
303 /// `Out2` UART Out2 signal; can be used as RI
/qemu/include/hw/arm/
H A Dfsl-imx25.h55 IMXSerialState uart[FSL_IMX25_NUM_UARTS]; member
93 * 0x43F9_0000 0x43F9_3FFF 16 Kbytes UART-1
94 * 0x43F9_4000 0x43F9_7FFF 16 Kbytes UART-2
109 * 0x5000_8000 0x5000_BFFF 16 Kbytes UART-4
110 * 0x5000_C000 0x5000_FFFF 16 Kbytes UART-3
117 * 0x5002_C000 0x5002_FFFF 16 Kbytes UART-5
H A Ddigic.h23 #include "hw/char/digic-uart.h"
40 DigicUartState uart; member
/qemu/docs/system/riscv/
H A Dshakti-c.rst24 * 1 UART
37 Shakti SDK can be used to generate the baremetal example UART applications.
56 Then we can run the UART example using:
/qemu/hw/m68k/
H A Dmcf5206.c167 DeviceState *uart[2]; member
175 /* Include the UART vector registers here. */
296 return mcf_uart_read(s->uart[0], offset - 0x140, size); in m5206_mbar_read()
298 return mcf_uart_read(s->uart[1], offset - 0x180, size); in m5206_mbar_read()
338 mcf_uart_write(s->uart[0], offset - 0x140, value, size); in m5206_mbar_write()
341 mcf_uart_write(s->uart[1], offset - 0x180, value, size); in m5206_mbar_write()
372 /* Not implemented: UART Output port bits. */ in m5206_mbar_write()
599 s->uart[0] = mcf_uart_create(s->pic[12], serial_hd(0)); in mcf5206_mbar_realize()
600 s->uart[1] = mcf_uart_create(s->pic[13], serial_hd(1)); in mcf5206_mbar_realize()

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