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Searched +full:ras +full:- +full:to +full:- +full:cas (Results 1 – 12 of 12) sorted by relevance

/linux-3.3/drivers/edac/
Di5000_edac.c12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
102 /* Non-Retry or redundant Retry errors */
275 /* Defines to extract the vaious fields from the
276 * MTRx - Memory Technology Registers
291 "8,192 - 13 rows",
292 "16,384 - 14 rows",
293 "32,768 - 15 rows",
298 "1,024 - 10 columns",
299 "2,048 - 11 columns",
300 "4,096 - 12 columns",
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Di5100_edac.c9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
13 * can not reflect this configuration so instead the chip-select
15 * the first half belonging to channel 0, the second half belonging
16 * to channel 1.
64 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
68 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
71 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
72 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
113 return a & ((1 << 8) - 1); in i5100_spddata_data()
119 return ((dti & ((1 << 4) - 1)) << 28) | in i5100_spdcmd_create()
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Di5400_edac.c18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
81 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
86 /* Non-fatal error register */
138 * Error masks are according with Table 5-17 of i5400 datasheet
142 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
143 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
146 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
148 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
150 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */
152 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
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Di7300_edac.c12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
18 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
50 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
51 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
52 * Each channel can have to 8 DIMM sets (called as SLOTS)
117 /* FIXME: Why do we need to have this static? */
152 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
153 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
155 * Each memory slot may have up to 2 AMB interfaces, one for income and another
156 * for outcome interface to the next slot.
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Dr82600_edac.c12 * Written with reference to 82600 High Integration Dual PCI System
14 * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
15 * references to this document given in []
35 * supports up to four banks of memory. The four banks can support a mix of
37 * each of which can be any size from 16MB to 512MB. Both registered (control
39 * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
50 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
75 * 1=Drive ECC bits to 0 during
82 * 2 CAS# Latency 0=3clks 1=2clks
84 * 1 RAS# to CAS# Delay 0=3 1=2
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Di82975x_edac.c34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
37 * 31:7 128 byte cache-line address
50 * More - See Page 65 of Intel DocSheet.
58 * 9 non-DRAM lock error (ndlock)
76 * 9 non-DRAM lock error (ndlock)
105 * 31:14 Base Addr of 16K memory-mapped
108 * 0 mem-mapped config space enable
111 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
118 * 7 set to 1 in highest DRB of
122 * 1:0 set to 0
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/linux-3.3/arch/sparc/kernel/
Dpci_sabre.c51 #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
111 #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
112 #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
115 #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry …
134 #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
136 #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
137 #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
138 #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
139 #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
140 #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */
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/linux-3.3/arch/arm/mach-ks8695/include/mach/
Dregs-mem.h2 * arch/arm/mach-ks8695/include/mach/regs-mem.h
6 * KS8695 - Memory Controller registers and bit definitions
72 #define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */
73 #define SDGCON_SDCAS (3 << 0) /* CAS latency */
/linux-3.3/arch/mn10300/include/asm/
Dbusctl-regs.h1 /* AM33v2 on-board bus controller registers
15 #include <asm/cpu-regs.h>
21 #define BCCR_B0AD 0x00000003 /* block 0 (80000000-83ffffff) bus allocation */
22 #define BCCR_B1AD 0x0000000c /* block 1 (84000000-87ffffff) bus allocation */
23 #define BCCR_B2AD 0x00000030 /* block 2 (88000000-8bffffff) bus allocation */
24 #define BCCR_B3AD 0x000000c0 /* block 3 (8c000000-8fffffff) bus allocation */
25 #define BCCR_B4AD 0x00000300 /* block 4 (90000000-93ffffff) bus allocation */
26 #define BCCR_B5AD 0x00000c00 /* block 5 (94000000-97ffffff) bus allocation */
27 #define BCCR_B6AD 0x00003000 /* block 6 (98000000-9bffffff) bus allocation */
28 #define BCCR_B7AD 0x0000c000 /* block 7 (9c000000-9fffffff) bus allocation */
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/linux-3.3/arch/sh/boards/
Dboard-magicpanelr2.c8 * This file is subject to the terms and conditions of the GNU General Public
58 /* CS2: LAN (0x08000000 - 0x0bffffff) */ in setup_chip_select()
64 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ in setup_chip_select()
70 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ in setup_chip_select()
76 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ in setup_chip_select()
82 /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ in setup_chip_select()
126 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); in setup_port_multiplexing()
263 .id = -1,
285 .id = -1,
294 /* Reserved for bootloader, read-only */
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/linux-3.3/arch/arm/mach-sa1100/include/mach/
DSA-1100.h2 * FILE SA-1100.h
8 * System StrongARM SA-1100
10 * Purpose Definition of constants related to the StrongARM
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
13 * StrongARM SA-1100 data sheet version 2.2.
20 #error You must include hardware.h not SA-1100.h
26 * SA1100 CS line to physical address
90 * Controller (UDC) Control/Status register end-point 0
93 * Controller (UDC) Control/Status register end-point 1
96 * Controller (UDC) Control/Status register end-point 2
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/linux-3.3/drivers/pinctrl/
Dpinctrl-u300.c5 * Copyright (C) 2009-2011 ST-Ericsson AB
11 * are connected to different pins in different packaging types, so it would
165 #define DRIVER_NAME "pinmux-u300"
543 PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
552 PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
657 * @dev: a pointer back to containing device
658 * @virtbase: the offset to the controller in virtual memory
669 * u300_pmx_registers - the array of registers read/written for each pinmux
681 * struct u300_pin_group - describes a U300 pin group
684 * from the driver-local pin enumeration space
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