include/asm/busctl-regs.h

1 /* AM33v2 on-board bus controller registers
15 #include <asm/cpu-regs.h>
21 #define BCCR_B0AD		0x00000003	/* block 0 (80000000-83ffffff) bus allocation */
22 #define BCCR_B1AD		0x0000000c	/* block 1 (84000000-87ffffff) bus allocation */
23 #define BCCR_B2AD		0x00000030	/* block 2 (88000000-8bffffff) bus allocation */
24 #define BCCR_B3AD		0x000000c0	/* block 3 (8c000000-8fffffff) bus allocation */
25 #define BCCR_B4AD		0x00000300	/* block 4 (90000000-93ffffff) bus allocation */
26 #define BCCR_B5AD		0x00000c00	/* block 5 (94000000-97ffffff) bus allocation */
27 #define BCCR_B6AD		0x00003000	/* block 6 (98000000-9bffffff) bus allocation */
28 #define BCCR_B7AD		0x0000c000	/* block 7 (9c000000-9fffffff) bus allocation */
29 #define BCCR_BxAD_EXBUS		0x0		/* - direct to system bus controller */
30 #define BCCR_BxAD_OPEXBUS	0x1		/* - direct to memory bus controller */
31 #define BCCR_BxAD_OCMBUS	0x2		/* - direct to on chip memory */
33 #define BCCR_API_DMACICD	0x00000000	/* - DMA > CI > CD */
34 #define BCCR_API_DMACDCI	0x00010000	/* - DMA > CD > CI */
35 #define BCCR_API_CICDDMA	0x00020000	/* - CI > CD > DMA */
36 #define BCCR_API_CDCIDMA	0x00030000	/* - CD > CI > DMA */
37 #define BCCR_API_ROUNDROBIN	0x00040000	/* - round robin */
39 #define BCCR_BEPRI_DMACDCI	0x00000000	/* - DMA > CI > CD */
40 #define BCCR_BEPRI_CICDDMA	0x00400000	/* - DMA > CD > CI */
41 #define BCCR_BEPRI_CDCIDMA	0x00800000	/* - CI > CD > DMA */
42 #define BCCR_BEPRI		0x00c00000	/* - CD > CI > DMA */
44 #define BCCR_TMON_16IOCLK	0x00000000	/* - 16 IOCLK cycles */
45 #define BCCR_TMON_256IOCLK	0x01000000	/* - 256 IOCLK cycles */
46 #define BCCR_TMON_4096IOCLK	0x02000000	/* - 4096 IOCLK cycles */
47 #define BCCR_TMON_65536IOCLK	0x03000000	/* - 65536 IOCLK cycles */
52 #define BCBERR_BESB_MON		0x00000001	/* - monitor space */
53 #define BCBERR_BESB_IO		0x00000002	/* - IO bus */
54 #define BCBERR_BESB_EX		0x00000004	/* - EX bus */
55 #define BCBERR_BESB_OPEX	0x00000008	/* - OpEX bus */
56 #define BCBERR_BESB_OCM		0x00000010	/* - on chip memory */
58 #define BCBERR_BERW_WRITE	0x00000000	/* - write */
59 #define BCBERR_BERW_READ	0x00000100	/* - read */
61 #define BCBERR_BESD_BCU		0x00000000	/* - BCU detected error */
62 #define BCBERR_BESD_SLAVE_BUS	0x00000200	/* - slave bus detected error */
64 #define BCBERR_BEBST_SINGLE	0x00000000	/* - single */
65 #define BCBERR_BEBST_BURST	0x00000400	/* - burst */
68 #define BCBERR_BEMR_NOERROR	0x00000000	/* - no error */
69 #define BCBERR_BEMR_CI		0x00001000	/* - CPU instruction fetch bus caused error */
70 #define BCBERR_BEMR_CD		0x00002000	/* - CPU data bus caused error */
71 #define BCBERR_BEMR_DMA		0x00004000	/* - DMA bus caused error */
101 #define SBCNTRL2_WM_FIXEDWAIT	0x00000000	/* - fixed wait access */
102 #define SBCNTRL2_WM_HANDSHAKE	0x01000000	/* - handshake access */
104 #define SBCNTRL2_BM_SYNC	0x00000000	/* - synchronous mode */
105 #define SBCNTRL2_BM_ASYNC	0x02000000	/* - asynchronous mode */
107 #define SBCNTRL2_BW_32		0x00000000	/* - 32 bits */
108 #define SBCNTRL2_BW_16		0x04000000	/* - 16 bits */
110 #define SBCNTRL2_RWINV_NORM	0x00000000	/* - normal (read high) */
111 #define SBCNTRL2_RWINV_INV	0x08000000	/* - inverted (read low) */
113 #define SBCNTRL2_BT_SRAM	0x00000000	/* - SRAM interface */
114 #define SBCNTRL2_BT_ADMUX	0x00000000	/* - addr/data multiplexed interface */
115 #define SBCNTRL2_BT_BROM	0x00000000	/* - burst ROM interface */
130 #define SDRAMBUS_SELFREQ	0x00000080	/* self-refresh mode request */
131 #define SDRAMBUS_SELFON		0x00000100	/* self-refresh mode on */
141 #define SDRAMBUS_RASLATE	0x30000000	/* RAS latency */
142 #define SDRAMBUS_CASLATE	0xc0000000	/* CAS latency */