Lines Matching +full:ras +full:- +full:to +full:- +full:cas
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
37 * 31:7 128 byte cache-line address
50 * More - See Page 65 of Intel DocSheet.
58 * 9 non-DRAM lock error (ndlock)
76 * 9 non-DRAM lock error (ndlock)
105 * 31:14 Base Addr of 16K memory-mapped
108 * 0 mem-mapped config space enable
111 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
118 * 7 set to 1 in highest DRB of
122 * 1:0 set to 0
135 * defines the PAGE SIZE to be used
155 #define I82975X_BNKARC 0x10e /* Type of device in each rank - Bank Arch (16b)
175 * 28:11 reserved, according to Intel
178 * seems to be ECC mode
243 pdev = to_pci_dev(mci->dev); in i82975x_get_error_info()
246 * This is a mess because there is no atomic way to read all the in i82975x_get_error_info()
250 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts); in i82975x_get_error_info()
251 pci_read_config_dword(pdev, I82975X_EAP, &info->eap); in i82975x_get_error_info()
252 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap); in i82975x_get_error_info()
253 pci_read_config_byte(pdev, I82975X_DES, &info->des); in i82975x_get_error_info()
254 pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn); in i82975x_get_error_info()
255 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2); in i82975x_get_error_info()
265 if (!(info->errsts2 & 0x0003)) in i82975x_get_error_info()
268 if ((info->errsts ^ info->errsts2) & 0x0003) { in i82975x_get_error_info()
269 pci_read_config_dword(pdev, I82975X_EAP, &info->eap); in i82975x_get_error_info()
270 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap); in i82975x_get_error_info()
271 pci_read_config_byte(pdev, I82975X_DES, &info->des); in i82975x_get_error_info()
273 &info->derrsyn); in i82975x_get_error_info()
283 if (!(info->errsts2 & 0x0003)) in i82975x_process_error_info()
289 if ((info->errsts ^ info->errsts2) & 0x0003) { in i82975x_process_error_info()
291 info->errsts = info->errsts2; in i82975x_process_error_info()
294 page = (unsigned long) info->eap; in i82975x_process_error_info()
296 if (info->xeap & 1) in i82975x_process_error_info()
298 page >>= (PAGE_SHIFT - 1); in i82975x_process_error_info()
301 if (row == -1) { in i82975x_process_error_info()
306 (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page); in i82975x_process_error_info()
309 chan = (mci->csrows[row].nr_channels == 1) ? 0 : info->eap & 1; in i82975x_process_error_info()
310 offst = info->eap in i82975x_process_error_info()
311 & ((1 << PAGE_SHIFT) - in i82975x_process_error_info()
312 (1 << mci->csrows[row].grain)); in i82975x_process_error_info()
314 if (info->errsts & 0x0002) in i82975x_process_error_info()
317 edac_mc_handle_ce(mci, page, offst, info->derrsyn, row, in i82975x_process_error_info()
327 debugf1("MC%d: %s()\n", mci->mc_idx, __func__); in i82975x_check()
336 * We treat interleaved-symmetric configuration as dual-channel - EAP's in dual_channel_active()
337 * bit-0 giving the channel of the error location. in dual_channel_active()
339 * All other configurations are treated as single channel - the EAP's in dual_channel_active()
340 * bit-0 will resolve ok in symmetric area of mixed in dual_channel_active()
387 for (index = 0; index < mci->nr_csrows; index++) { in i82975x_init_csrows()
388 csrow = &mci->csrows[index]; in i82975x_init_csrows()
393 cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT); in i82975x_init_csrows()
398 if (csrow->nr_channels > 1) in i82975x_init_csrows()
406 * [0-7] for single-channel; i.e. csrow->nr_channels = 1 in i82975x_init_csrows()
407 * [0-3] for dual-channel; i.e. csrow->nr_channels = 2 in i82975x_init_csrows()
409 for (chan = 0; chan < csrow->nr_channels; chan++) in i82975x_init_csrows()
410 strncpy(csrow->channels[chan].label, in i82975x_init_csrows()
417 csrow->first_page = last_cumul_size; in i82975x_init_csrows()
418 csrow->last_page = cumul_size - 1; in i82975x_init_csrows()
419 csrow->nr_pages = cumul_size - last_cumul_size; in i82975x_init_csrows()
421 csrow->grain = 1 << 7; /* 128Byte cache-line resolution */ in i82975x_init_csrows()
422 csrow->mtype = MEM_DDR2; /* I82975x supports only DDR2 */ in i82975x_init_csrows()
423 csrow->dtype = i82975x_dram_type(mch_window, index); in i82975x_init_csrows()
424 csrow->edac_mode = EDAC_SECDED; /* only supported */ in i82975x_init_csrows()
435 * (shows 13-5-5-5 for 800-DDR2) in i82975x_print_dram_timings()
436 * Asus P5W Bios reports 15-5-4-4 in i82975x_print_dram_timings()
445 " RAS Active Min = %d %d\n" in i82975x_print_dram_timings()
446 " CAS latency = %d %d\n" in i82975x_print_dram_timings()
447 " RAS to CAS = %d %d\n" in i82975x_print_dram_timings()
448 " RAS precharge = %d %d\n", in i82975x_print_dram_timings()
464 int rc = -ENODEV; in i82975x_probe1()
537 rc = -ENOMEM; in i82975x_probe1()
542 mci->dev = &pdev->dev; in i82975x_probe1()
543 mci->mtype_cap = MEM_FLAG_DDR2; in i82975x_probe1()
544 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; in i82975x_probe1()
545 mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; in i82975x_probe1()
546 mci->mod_name = EDAC_MOD_STR; in i82975x_probe1()
547 mci->mod_ver = I82975X_REVISION; in i82975x_probe1()
548 mci->ctl_name = i82975x_devs[dev_idx].ctl_name; in i82975x_probe1()
549 mci->dev_name = pci_name(pdev); in i82975x_probe1()
550 mci->edac_check = i82975x_check; in i82975x_probe1()
551 mci->ctl_page_to_phys = NULL; in i82975x_probe1()
553 pvt = (struct i82975x_pvt *) mci->pvt_info; in i82975x_probe1()
554 pvt->mch_window = mch_window; in i82975x_probe1()
556 mci->scrub_mode = SCRUB_HW_SRC; in i82975x_probe1()
587 return -EIO; in i82975x_init_one()
589 rc = i82975x_probe1(pdev, ent->driver_data); in i82975x_init_one()
604 mci = edac_mc_del_mc(&pdev->dev); in i82975x_remove_one()
608 pvt = mci->pvt_info; in i82975x_remove_one()
609 if (pvt->mch_window) in i82975x_remove_one()
610 iounmap( pvt->mch_window ); in i82975x_remove_one()
653 pci_rc = -ENODEV; in i82975x_init()
661 pci_rc = -ENODEV; in i82975x_init()