Lines Matching +full:ras +full:- +full:to +full:- +full:cas
12 * Written with reference to 82600 High Integration Dual PCI System
14 * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
15 * references to this document given in []
35 * supports up to four banks of memory. The four banks can support a mix of
37 * each of which can be any size from 16MB to 512MB. Both registered (control
39 * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
50 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
75 * 1=Drive ECC bits to 0 during
82 * 2 CAS# Latency 0=3clks 1=2clks
84 * 1 RAS# to CAS# Delay 0=3 1=2
86 * 0 RAS# Precharge 0=3 1=2
126 * 7:0 Address lines 30:24 - upper limit of
143 pdev = to_pci_dev(mci->dev); in r82600_get_error_info()
144 pci_read_config_dword(pdev, R82600_EAP, &info->eapr); in r82600_get_error_info()
146 if (info->eapr & BIT(0)) in r82600_get_error_info()
147 /* Clear error to allow next error to be reported [p.62] */ in r82600_get_error_info()
152 if (info->eapr & BIT(1)) in r82600_get_error_info()
153 /* Clear error to allow next error to be reported [p.62] */ in r82600_get_error_info()
170 eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13; in r82600_process_error_info()
172 syndrome = (info->eapr >> 4) & 0xFF; in r82600_process_error_info()
178 if (info->eapr & BIT(0)) { /* CE? */ in r82600_process_error_info()
185 0, mci->ctl_name); in r82600_process_error_info()
188 if (info->eapr & BIT(1)) { /* UE? */ in r82600_process_error_info()
195 mci->ctl_name); in r82600_process_error_info()
205 debugf1("MC%d: %s()\n", mci->mc_idx, __func__); in r82600_check()
228 for (index = 0; index < mci->nr_csrows; index++) { in r82600_init_csrows()
229 csrow = &mci->csrows[index]; in r82600_init_csrows()
248 csrow->first_page = row_base >> PAGE_SHIFT; in r82600_init_csrows()
249 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; in r82600_init_csrows()
250 csrow->nr_pages = csrow->last_page - csrow->first_page + 1; in r82600_init_csrows()
251 /* Error address is top 19 bits - so granularity is * in r82600_init_csrows()
253 csrow->grain = 1 << 14; in r82600_init_csrows()
254 csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR; in r82600_init_csrows()
255 /* FIXME - check that this is unknowable with this chipset */ in r82600_init_csrows()
256 csrow->dtype = DEV_UNKNOWN; in r82600_init_csrows()
259 csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; in r82600_init_csrows()
284 return -ENOMEM; in r82600_probe1()
287 mci->dev = &pdev->dev; in r82600_probe1()
288 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; in r82600_probe1()
289 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; in r82600_probe1()
290 /* FIXME try to work out if the chip leads have been used for COM2 in r82600_probe1()
294 /* On the R82600, the pins for memory bits 72:65 - i.e. the * in r82600_probe1()
298 mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; in r82600_probe1()
302 debugf3("%s(): mci = %p - Scrubbing disabled! EAP: " in r82600_probe1()
305 mci->edac_cap = EDAC_FLAG_NONE; in r82600_probe1()
307 mci->mod_name = EDAC_MOD_STR; in r82600_probe1()
308 mci->mod_ver = R82600_REVISION; in r82600_probe1()
309 mci->ctl_name = "R82600"; in r82600_probe1()
310 mci->dev_name = pci_name(pdev); in r82600_probe1()
311 mci->edac_check = r82600_check; in r82600_probe1()
312 mci->ctl_page_to_phys = NULL; in r82600_probe1()
317 * type of memory controller. The ID is therefore hardcoded to 0. in r82600_probe1()
333 r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); in r82600_probe1()
336 "%s(): Unable to create PCI control\n", in r82600_probe1()
348 return -ENODEV; in r82600_probe1()
357 /* don't need to call pci_enable_device() */ in r82600_init_one()
358 return r82600_probe1(pdev, ent->driver_data); in r82600_init_one()
370 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) in r82600_remove_one()
411 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "