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/qemu/target/loongarch/
H A DREADME1 - Introduction
3 LoongArch is the general processor architecture of Loongson.
7 …https://github.com/loongson/LoongArch-Documentation/releases/download/2021.08.17/LoongArch-Vol1-v1…
9 …We can get the latest loongarch documents at https://github.com/loongson/LoongArch-Documentation/t…
12 - System emulation
16 - Linux-user emulation
18 …We already support Linux user emulation. We can use LoongArch cross-tools to build LoongArch execu…
19 and We can also use qemu-loongarch64 to run LoongArch executables.
21 1. Config cross-tools env.
27 …./configure --static --prefix=/usr --disable-werror --target-list="loongarch64-linux-user" --en…
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H A Dcsr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2025 Loongson Technology Corporation Limited
9 #include "cpu-csr.h"
13 CSRFL_READONLY = (1 << 0),
14 CSRFL_EXITTB = (1 << 1),
15 CSRFL_IO = (1 << 2),
16 CSRFL_UNUSED = (1 << 3),
H A Dinternals.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * QEMU LoongArch CPU -- internal functions and types
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
37 TLBRET_BADADDR = 1,
/qemu/hw/mips/
H A Dloongson3_virt.c2 * Generic Loongson-3 Platform support
4 * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com)
5 * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
22 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
32 #include "hw/char/serial-mm.h"
45 #include "hw/pci-host/gpex.h"
52 #include "qemu/error-report.h"
59 * Loongson-3's virtual machine BIOS can be obtained here:
60 * 1, https://github.com/loongson-community/firmware-nonfree
66 #define RTC_IRQ 1
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H A Dfuloong2e.c4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
9 * Contributions after 2012-01-13 are licensed under the terms of the
14 * Fuloong 2e mini pc is based on ICT/ST Loongson 2e CPU (MIPS III like, 800MHz)
15 * https://www.linux-mips.org/wiki/Fuloong_2E
17 * Loongson 2e manuals:
18 * https://github.com/loongson-community/docs/tree/master/2E
36 #include "hw/qdev-properties.h"
42 #include "qemu/error-report.h"
55 * who want to build a pmon binary please first git-clone the source
57 * https://github.com/loongson-community/pmon
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/qemu/docs/system/loongarch/
H A Dvirt.rst12 -----------------
26 --------------------
28 The ``qemu-system-loongarch64`` provides emulation for virt
33 ------------
39 (1) Build qemu-system-loongarch64:
41 .. code-block:: bash
43 ./configure --target-list="loongarch64-softmmu"
44 make -j8
48 .. code-block:: bash
50 …wget https://github.com/loongson/build-tools/releases/download/2022.09.06/loongarch64-clfs-6.3-cro…
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/qemu/hw/loongarch/
H A Dvirt-fdt-build.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2025 Loongson Technology Corporation Limited
6 #include "qemu/error-report.h"
7 #include "qemu/guest-random.h"
10 #include "hw/core/sysbus-fdt.h"
14 #include "hw/pci-host/gpex.h"
15 #include "hw/pci-host/ls7a.h"
25 ms->fdt = create_device_tree(&lvms->fdt_size); in create_fdt()
26 if (!ms->fdt) { in create_fdt()
28 exit(1); in create_fdt()
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/qemu/hw/intc/
H A Dloongarch_pic_common.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * QEMU Loongson 7A1000 I/O interrupt controller.
4 * Copyright (C) 2024 Loongson Technology Corporation Limited
10 #include "hw/qdev-properties.h"
18 if (lpcc->pre_save) { in loongarch_pic_pre_save()
19 return lpcc->pre_save(s); in loongarch_pic_pre_save()
30 if (lpcc->post_load) { in loongarch_pic_post_load()
31 return lpcc->post_load(s, version_id); in loongarch_pic_post_load()
41 if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) { in loongarch_pic_common_realize()
53 * With Loongson 7A1000 user manual in loongarch_pic_common_reset_hold()
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H A Dloongson_ipi.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Loongson ipi interrupt support
5 * Copyright (C) 2021 Loongson Technology Corporation Limited
10 #include "hw/qdev-properties.h"
16 if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { in get_iocsr_as()
17 return &MIPS_CPU(cpu)->env.iocsr.as; in get_iocsr_as()
34 *index = cs->cpu_index; in loongson_cpu_by_arch_id()
63 lic->parent_realize(dev, &local_err); in loongson_ipi_realize()
69 if (sc->num_cpu == 0) { in loongson_ipi_realize()
70 error_setg(errp, "num-cpu must be at least 1"); in loongson_ipi_realize()
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H A Dloongarch_pch_msi.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * QEMU Loongson 7A1000 msi interrupt controller.
5 * Copyright (C) 2021 Loongson Technology Corporation Limited
43 irq_num = (val & 0xff) - s->irq_base; in loongarch_msi_mem_write()
45 assert(irq_num < s->irq_num); in loongarch_msi_mem_write()
46 qemu_set_irq(s->pch_msi_irq[irq_num], 1); in loongarch_msi_mem_write()
59 if (!s->irq_num || s->irq_num > PCH_MSI_IRQ_NUM) { in loongarch_pch_msi_realize()
64 s->pch_msi_irq = g_new(qemu_irq, s->irq_num); in loongarch_pch_msi_realize()
65 qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num); in loongarch_pch_msi_realize()
72 g_free(s->pch_msi_irq); in loongarch_pch_msi_unrealize()
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H A Dloongarch_extioi_common.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Loongson extioi interrupt controller emulation
4 * Copyright (C) 2024 Loongson Technology Corporation Limited
7 #include "qemu/error-report.h"
10 #include "hw/qdev-properties.h"
19 uint64_t arch_id = k->get_arch_id(CPU(dev)); in loongarch_extioi_get_cpu()
22 for (i = 0; i < s->num_cpu; i++) { in loongarch_extioi_get_cpu()
23 if (s->cpu[i].arch_id == arch_id) { in loongarch_extioi_get_cpu()
24 return &s->cpu[i]; in loongarch_extioi_get_cpu()
50 core->cpu = CPU(dev); in loongarch_extioi_cpu_plug()
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H A Dloongarch_pch_pic.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * QEMU Loongson 7A1000 I/O interrupt controller.
5 * Copyright (C) 2021 Loongson Technology Corporation Limited
24 val = mask & s->intirr & ~s->int_mask; in pch_pic_update_irq()
27 s->intisr |= MAKE_64BIT_MASK(irq, 1); in pch_pic_update_irq()
28 qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 1); in pch_pic_update_irq()
33 * do not clear pending irq for edge-triggered on lowering edge in pch_pic_update_irq()
35 val = mask & s->intisr & ~s->intirr; in pch_pic_update_irq()
38 s->intisr &= ~MAKE_64BIT_MASK(irq, 1); in pch_pic_update_irq()
39 qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 0); in pch_pic_update_irq()
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/qemu/tests/functional/
H A Dtest_mips64el_fuloong2e.py3 # Functional tests for the Lemote Fuloong-2E machine.
5 # Copyright (c) 2019 Philippe Mathieu-Daudé <f4bug@amsat.org>
8 # See the COPYING file in the top-level directory.
10 # SPDX-License-Identifier: GPL-2.0-or-later
25 'linux-image-3.16.0-6-loongson-2e_3.16.56-1+deb8u1_mipsel.deb'),
31 member='boot/vmlinux-3.16.0-6-loongson-2e')
36 self.vm.add_args('-kernel', kernel_path,
37 '-append', kernel_command_line)
47 # http://dev.lemote.com/files/resource/download/rescue/rescue-yl
52 assert checksum.decode("utf-8") == sha
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/qemu/target/mips/
H A Dmips-defs.h9 * ------------------------------------------------
12 * bits 0-23: MIPS base instruction sets
16 #define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
26 * bits 24-39: MIPS ASEs
36 * bits 40-51: vendor-specific base instruction sets
45 * bits 52-63: vendor-specific ASEs
51 /* Loongson MultiMedia Instructions */
53 /* Loongson EXTensions */
65 /* MIPS Technologies "Release 1" */
87 * - Disallow "special" instruction handling for PMON/SPIM.
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H A Dcpu-defs.c.inc4 * Copyright (c) 2004-2005 Jocelyn Mayer
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
31 ((1U << CP0C1_M) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
38 ((1U << CP0C2_M))
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
63 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
64 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
85 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
86 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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/qemu/linux-user/loongarch64/
H A Dtarget_signal.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2021 Loongson Technology Corporation Limited
11 #define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
H A Dtarget_syscall.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2021 Loongson Technology Corporation Limited
37 #define TARGET_MCL_CURRENT 1
/qemu/tests/tcg/loongarch64/system/
H A Dboot.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
18 .size _start, .-_start
32 .size _exit, .-_exit
44 addi.w t1, t1, -1
H A Dregdef.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2021 Loongson Technology Corporation Limited
12 #define v0 $r4 /* return value - caller saved */
77 #define STT_OBJECT 1
/qemu/target/mips/tcg/
H A Dloong-ext.decode1 # Loongson 64-bit Extension instructions
3 # Copyright (C) 2021 Philippe Mathieu-Daudé
5 # SPDX-License-Identifier: LGPL-2.1-or-later
17 MULTu_G 011100 ..... ..... ..... 00000 0100-0 @rs_rt_rd
18 DMULTu_G 011100 ..... ..... ..... 00000 0100-1 @rs_rt_rd
/qemu/include/hw/intc/
H A Dloongarch_pic_common.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (c) 2024 Loongson Technology Corporation Limited
10 #include "hw/pci-host/ls7a.h"
52 uint64_t htmsi_en; /* 0x040 1=msi */
53 uint64_t intedge; /* 0x060 edge=1 level=0 */
54 uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */
66 uint8_t route_entry[64]; /* 0x100 - 0x138 */
67 uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
H A Dloongarch_extioi_common.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2024 Loongson Technology Corporation Limited
27 #define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
28 #define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
29 #define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
30 #define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
31 #define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
32 #define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
33 #define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
34 #define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
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/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_fcmp.c.inc1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2021 Loongson Technology Corporation Limited
11 /*check cond , cond =[0-8,10,12] */
13 return -1;
34 uint32_t flags = get_fcmp_flags(ctx, a->fcond >>1);
37 if (flags == -1) {
49 src1 = get_fpr(ctx, a->fj);
50 src2 = get_fpr(ctx, a->fk);
51 fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
54 tcg_gen_st8_tl(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd]));
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H A Dtrans_extra.c.inc1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2021 Loongson Technology Corporation Limited
20 TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
21 TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
33 TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
34 TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
47 TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
48 TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
50 translator_io_start(&ctx->base);
62 return gen_rdtime(ctx, a, 1, 0);
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/qemu/target/loongarch/tcg/
H A Dconstant_timer.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
12 #include "cpu-csr.h"
28 expire = timer_expire_time_ns(&cpu->timer); in cpu_loongarch_get_constant_timer_ticks()
30 return (expire - now) / TIMER_PERIOD; in cpu_loongarch_get_constant_timer_ticks()
36 CPULoongArchState *env = &cpu->env; in cpu_loongarch_store_constant_timer_config()
39 env->CSR_TCFG = value; in cpu_loongarch_store_constant_timer_config()
43 timer_mod(&cpu->timer, next); in cpu_loongarch_store_constant_timer_config()
45 timer_del(&cpu->timer); in cpu_loongarch_store_constant_timer_config()
52 CPULoongArchState *env = &cpu->env; in loongarch_constant_timer_cb()
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