1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch 7A1000 I/O interrupt controller definitions 4 * Copyright (c) 2024 Loongson Technology Corporation Limited 5 */ 6 7 #ifndef HW_LOONGARCH_PIC_COMMON_H 8 #define HW_LOONGARCH_PIC_COMMON_H 9 10 #include "hw/pci-host/ls7a.h" 11 #include "hw/sysbus.h" 12 13 #define PCH_PIC_INT_ID 0x00 14 #define PCH_PIC_INT_ID_VAL 0x7 15 #define PCH_PIC_INT_ID_VER 0x1 16 #define PCH_PIC_INT_MASK 0x20 17 #define PCH_PIC_HTMSI_EN 0x40 18 #define PCH_PIC_INT_EDGE 0x60 19 #define PCH_PIC_INT_CLEAR 0x80 20 #define PCH_PIC_AUTO_CTRL0 0xc0 21 #define PCH_PIC_AUTO_CTRL1 0xe0 22 #define PCH_PIC_ROUTE_ENTRY 0x100 23 #define PCH_PIC_ROUTE_ENTRY_END 0x13f 24 #define PCH_PIC_HTMSI_VEC 0x200 25 #define PCH_PIC_HTMSI_VEC_END 0x23f 26 #define PCH_PIC_INT_STATUS 0x3a0 27 #define PCH_PIC_INT_POL 0x3e0 28 29 #define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common" 30 OBJECT_DECLARE_TYPE(LoongArchPICCommonState, 31 LoongArchPICCommonClass, LOONGARCH_PIC_COMMON) 32 33 union LoongArchPIC_ID { 34 struct { 35 uint8_t _reserved_0[3]; 36 uint8_t id; 37 uint8_t version; 38 uint8_t _reserved_1; 39 uint8_t irq_num; 40 uint8_t _reserved_2; 41 } QEMU_PACKED desc; 42 uint64_t data; 43 }; 44 45 struct LoongArchPICCommonState { 46 SysBusDevice parent_obj; 47 48 qemu_irq parent_irq[64]; 49 union LoongArchPIC_ID id; /* 0x00 interrupt ID register */ 50 uint64_t int_mask; /* 0x020 interrupt mask register */ 51 uint64_t htmsi_en; /* 0x040 1=msi */ 52 uint64_t intedge; /* 0x060 edge=1 level=0 */ 53 uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */ 54 uint64_t auto_crtl0; /* 0x0c0 */ 55 uint64_t auto_crtl1; /* 0x0e0 */ 56 uint64_t last_intirr; /* edge detection */ 57 uint64_t intirr; /* 0x380 interrupt request register */ 58 uint64_t intisr; /* 0x3a0 interrupt service register */ 59 /* 60 * 0x3e0 interrupt level polarity selection 61 * register 0 for high level trigger 62 */ 63 uint64_t int_polarity; 64 65 uint8_t route_entry[64]; /* 0x100 - 0x138 */ 66 uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */ 67 68 MemoryRegion iomem; 69 unsigned int irq_num; 70 }; 71 72 struct LoongArchPICCommonClass { 73 SysBusDeviceClass parent_class; 74 75 DeviceRealize parent_realize; 76 ResettablePhases parent_phases; 77 int (*pre_save)(LoongArchPICCommonState *s); 78 int (*post_load)(LoongArchPICCommonState *s, int version_id); 79 }; 80 #endif /* HW_LOONGARCH_PIC_COMMON_H */ 81