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/qemu/hw/adc/
H A Daspeed_adc.c117 qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: " in aspeed_adc_engine_read()
125 qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: " in aspeed_adc_engine_read()
143 qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: " in aspeed_adc_engine_read()
158 qemu_log_mask(LOG_UNIMP, "%s: engine[%u]: 0x%" HWADDR_PRIx "\n", in aspeed_adc_engine_read()
192 qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: " in aspeed_adc_engine_write()
200 qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: " in aspeed_adc_engine_write()
212 qemu_log_mask(LOG_GUEST_ERROR, "%s: engine[%u]: " in aspeed_adc_engine_write()
228 qemu_log_mask(LOG_UNIMP, "%s: engine[%u]: " in aspeed_adc_engine_write()
290 DEFINE_PROP_UINT32("engine-id", AspeedADCEngineState, engine_id, 0),
301 dc->desc = "Aspeed Analog-to-Digital Engine"; in aspeed_adc_engine_class_init()
[all …]
H A Dtrace-events7 aspeed_adc_engine_read(uint32_t engine_id, uint64_t addr, uint64_t value) "engine[%u] 0x%" PRIx64 "…
8 aspeed_adc_engine_write(uint32_t engine_id, uint64_t addr, uint64_t value) "engine[%u] 0x%" PRIx64 …
/qemu/tests/qtest/
H A Dpnv-host-i2c-test.c35 int engine; member
48 (PNV10_XSCOM_I2CM_SIZE * ctlr->engine) + reg); in pnv_i2c_xscom_addr()
370 int engine; in check_i2cm_por_regs() local
371 for (engine = 0; engine < chip->num_i2c; engine++) { in check_i2cm_por_regs()
375 ctlr.engine = engine; in check_i2cm_por_regs()
391 int engine; in reset_all() local
392 for (engine = 0; engine < chip->num_i2c; engine++) { in reset_all()
396 ctlr.engine = engine; in reset_all()
440 ctlr.engine = 2; in test_host_i2c()
H A Daspeed-hace-utils.c2 * QTest testcase for the ASPEED Hash and Crypto Engine
176 /* Check engine is idle, no busy or irq bits set */ in aspeed_test_md5()
210 /* Check engine is idle, no busy or irq bits set */ in aspeed_test_sha256()
244 /* Check engine is idle, no busy or irq bits set */ in aspeed_test_sha384()
278 /* Check engine is idle, no busy or irq bits set */ in aspeed_test_sha512()
323 /* Check engine is idle, no busy or irq bits set */ in aspeed_test_sha256_sg()
374 /* Check engine is idle, no busy or irq bits set */ in aspeed_test_sha384_sg()
425 /* Check engine is idle, no busy or irq bits set */ in aspeed_test_sha512_sg()
470 /* Check engine is idle, no busy or irq bits set */ in aspeed_test_sha256_accum()
511 /* Check engine is idle, no busy or irq bits set */ in aspeed_test_sha384_accum()
[all …]
H A Dbcm2835-dma-test.c2 * QTest testcase for BCM283x DMA engine (on Raspberry Pi 3)
19 /* DMA engine registers: */
/qemu/docs/devel/migration/
H A Dqpl-compression.rst97 #accel-config config-engine iax1/engine1.0 -g 0
98 #accel-config config-engine iax1/engine1.1 -g 0
99 #accel-config config-engine iax1/engine1.2 -g 0
100 #accel-config config-engine iax1/engine1.3 -g 0
101 #accel-config config-engine iax1/engine1.4 -g 0
102 #accel-config config-engine iax1/engine1.5 -g 0
103 #accel-config config-engine iax1/engine1.6 -g 0
104 #accel-config config-engine iax1/engine1.7 -g 0
/qemu/docs/devel/testing/
H A Dblkdebug.rst10 The ``blkdebug`` block driver is a rule-based error injection engine. It can be
29 engine when to fail an I/O request.
63 (optional) the engine must be in this state number in order for this
123 The error injection engine has an integer called the "state" that always starts
159 (optional) the engine must be in this state number in order for this
/qemu/tests/migration-stress/guestperf/
H A Dshell.py30 from guestperf.engine import Engine
70 return Engine(binary=args.binary,
186 engine = self.get_engine(args)
191 report = engine.run(hardware, scenario)
222 engine = self.get_engine(args)
242 report = engine.run(hardware, scenario)
/qemu/docs/specs/
H A Dfsi.rst6 master/slave and the end engine.
33 driving CFAM engine accesses into the POWER chip. At the hardware level
50 CFAM's LBUS. Engine implementations should subclass the LBusDevice and set the
51 'config' member of LBusDeviceClass to match the engine's type.
H A Dppc-xive.rst7 Engine".
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
187 the IVPE sub-engine which does a CAM scan to find a CPU to deliver the
/qemu/include/hw/dma/
H A Dxlnx_csu_dma.h60 * read: Start a read transfer on a Xilinx CSU DMA engine
62 * @s: the Xilinx CSU DMA engine to start the transfer on
/qemu/include/hw/ssi/
H A Dpnv_spi.h15 * SPI Controller has sequencer and shift engine. The SPI shift engine
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h113 #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
114 #define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */
115 #define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */
116 #define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */
117 #define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */
118 #define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
119 #define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
120 #define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
121 #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
122 #define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
[all …]
/qemu/hw/ppc/
H A Dpnv_i2c.c460 i2c->engine, index); in pnv_i2c_bus_dt_xscom()
476 (i2c->engine - 1) * PNV9_XSCOM_I2CM_SIZE; in pnv_i2c_dt_xscom()
493 _FDT((fdt_setprop_cell(fdt, i2c_offset, "chip-engine#", i2c->engine))); in pnv_i2c_dt_xscom()
548 DEFINE_PROP_UINT32("engine", PnvI2C, engine, 1),
/qemu/hw/misc/
H A Dexynos4210_rng.c120 /* PRNG engine chosen? */ in exynos4210_rng_run_engine()
125 /* PRNG engine started? */ in exynos4210_rng_run_engine()
139 /* Always clear start engine bit */ in exynos4210_rng_run_engine()
H A Daspeed_hace.c2 * ASPEED Hash and Crypto Engine
659 dc->desc = "AST2400 Hash and Crypto Engine"; in aspeed_ast2400_hace_class_init()
679 dc->desc = "AST2500 Hash and Crypto Engine"; in aspeed_ast2500_hace_class_init()
699 dc->desc = "AST2600 Hash and Crypto Engine"; in aspeed_ast2600_hace_class_init()
719 dc->desc = "AST1030 Hash and Crypto Engine"; in aspeed_ast1030_hace_class_init()
739 dc->desc = "AST2700 Hash and Crypto Engine"; in aspeed_ast2700_hace_class_init()
H A Dallwinner-h3-ccu.c38 REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
54 REG_PLL_DE_BIAS = 0x0248, /* PLL Display Engine Bias */
137 case REG_PLL_DE: /* PLL Display Engine Control */ in allwinner_h3_ccu_write()
/qemu/scripts/coverity-scan/
H A Drun-coverity-scan34 # --docker-engine : specify the container engine to use (docker/podman/auto);
120 tests/docker/docker.py --engine ${DOCKER_ENGINE} build \
250 --docker-engine)
253 echo "--docker-engine needs an argument"
/qemu/tests/docker/
H A Ddocker.py75 """ Guess a working engine command or raise exception if not found"""
92 raise Exception("Cannot find working engine command. Tried:\n%s" %
667 parser.add_argument("--engine", type=EngineEnum.argparse, choices=list(EngineEnum),
668 help="specify which container engine to use")
677 if args.engine:
678 USE_ENGINE = args.engine
/qemu/include/hw/misc/
H A Daspeed_scu.h101 * 31 Enable Video Engine clock dynamic slow down
102 * 30:28 Video Engine clock slow down setting
103 * 27 2D Engine GCLK clock source selection
104 * 26 2D Engine GCLK clock throttling enable
/qemu/hw/ide/
H A Dahci-internal.h171 #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
172 #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
173 #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
177 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
/qemu/hw/fsi/
H A Dcfam.c56 * future engines from address 0x10 onwards. Returning 0 as engine in fsi_cfam_config_read()
139 /* Add scratchpad engine */ in fsi_cfam_realize()
/qemu/include/hw/ppc/
H A Dpnv_adu.h23 /* LPCMC (LPC Master Controller) access engine */
H A Dpnv_i2c.h29 uint32_t engine; member
/qemu/include/system/
H A Devent-loop-base.h33 /* AioContext AIO engine parameters */

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