135593573SXuzhou Cheng /* 235593573SXuzhou Cheng * Xilinx Platform CSU Stream DMA emulation 335593573SXuzhou Cheng * 435593573SXuzhou Cheng * This implementation is based on 535593573SXuzhou Cheng * https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c 635593573SXuzhou Cheng * 735593573SXuzhou Cheng * This program is free software; you can redistribute it and/or 835593573SXuzhou Cheng * modify it under the terms of the GNU General Public License as 935593573SXuzhou Cheng * published by the Free Software Foundation; either version 2 or 1035593573SXuzhou Cheng * (at your option) version 3 of the License. 1135593573SXuzhou Cheng * 1235593573SXuzhou Cheng * This program is distributed in the hope that it will be useful, 1335593573SXuzhou Cheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 1435593573SXuzhou Cheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1535593573SXuzhou Cheng * GNU General Public License for more details. 1635593573SXuzhou Cheng * 1735593573SXuzhou Cheng * You should have received a copy of the GNU General Public License along 1835593573SXuzhou Cheng * with this program; if not, see <http://www.gnu.org/licenses/>. 1935593573SXuzhou Cheng */ 2035593573SXuzhou Cheng 2135593573SXuzhou Cheng #ifndef XLNX_CSU_DMA_H 2235593573SXuzhou Cheng #define XLNX_CSU_DMA_H 2335593573SXuzhou Cheng 24ba4fbdbdSFrancisco Iglesias #include "hw/sysbus.h" 25ba4fbdbdSFrancisco Iglesias #include "hw/register.h" 26ba4fbdbdSFrancisco Iglesias #include "hw/ptimer.h" 27ba4fbdbdSFrancisco Iglesias #include "hw/stream.h" 28ba4fbdbdSFrancisco Iglesias 2935593573SXuzhou Cheng #define TYPE_XLNX_CSU_DMA "xlnx.csu_dma" 3035593573SXuzhou Cheng 3135593573SXuzhou Cheng #define XLNX_CSU_DMA_R_MAX (0x2c / 4) 3235593573SXuzhou Cheng 3335593573SXuzhou Cheng typedef struct XlnxCSUDMA { 3435593573SXuzhou Cheng SysBusDevice busdev; 3535593573SXuzhou Cheng MemoryRegion iomem; 3635593573SXuzhou Cheng MemTxAttrs attr; 3735593573SXuzhou Cheng MemoryRegion *dma_mr; 38c31b7f59SPhilippe Mathieu-Daudé AddressSpace dma_as; 3935593573SXuzhou Cheng qemu_irq irq; 4035593573SXuzhou Cheng StreamSink *tx_dev; /* Used as generic StreamSink */ 4135593573SXuzhou Cheng ptimer_state *src_timer; 4235593573SXuzhou Cheng 4335593573SXuzhou Cheng uint16_t width; 4435593573SXuzhou Cheng bool is_dst; 4535593573SXuzhou Cheng bool r_size_last_word; 4635593573SXuzhou Cheng 4735593573SXuzhou Cheng StreamCanPushNotifyFn notify; 4835593573SXuzhou Cheng void *notify_opaque; 4935593573SXuzhou Cheng 5035593573SXuzhou Cheng uint32_t regs[XLNX_CSU_DMA_R_MAX]; 5135593573SXuzhou Cheng RegisterInfo regs_info[XLNX_CSU_DMA_R_MAX]; 5235593573SXuzhou Cheng } XlnxCSUDMA; 5335593573SXuzhou Cheng 54*00f05c02SFrancisco Iglesias OBJECT_DECLARE_TYPE(XlnxCSUDMA, XlnxCSUDMAClass, XLNX_CSU_DMA) 55*00f05c02SFrancisco Iglesias 56*00f05c02SFrancisco Iglesias struct XlnxCSUDMAClass { 57*00f05c02SFrancisco Iglesias SysBusDeviceClass parent_class; 58*00f05c02SFrancisco Iglesias 59*00f05c02SFrancisco Iglesias /* 60*00f05c02SFrancisco Iglesias * read: Start a read transfer on a Xilinx CSU DMA engine 61*00f05c02SFrancisco Iglesias * 62*00f05c02SFrancisco Iglesias * @s: the Xilinx CSU DMA engine to start the transfer on 63*00f05c02SFrancisco Iglesias * @addr: the address to read 64*00f05c02SFrancisco Iglesias * @len: the number of bytes to read at 'addr' 65*00f05c02SFrancisco Iglesias * 66*00f05c02SFrancisco Iglesias * @return a MemTxResult indicating whether the operation succeeded ('len' 67*00f05c02SFrancisco Iglesias * bytes were read) or failed. 68*00f05c02SFrancisco Iglesias */ 69*00f05c02SFrancisco Iglesias MemTxResult (*read)(XlnxCSUDMA *s, hwaddr addr, uint32_t len); 70*00f05c02SFrancisco Iglesias }; 7135593573SXuzhou Cheng 7235593573SXuzhou Cheng #endif 73