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/qemu/docs/devel/
H A Ds390-dasd-ipl.rst1 Booting from real channel-attached devices on s390x
22 and the TIC (Transfer In Channel) will transfer control to the channel
23 program contained in the IPL2 data. The TIC channel command is the
24 equivalent of a branch/jump/goto instruction for channel programs.
29 The TIC ccw instruction at the end of the IPL1 channel program will begin
30 the execution of the IPL2 channel program. IPL2 is stage-2 of the boot
31 process and will contain a larger channel program than IPL1. The point of
39 NOTE: The IPL2 channel program might read data into memory
40 location ``0x0`` thereby overwriting the IPL1 psw and channel program. This is ok
58 off the reading of IPL1 data. Since the channel program from IPL1 will be
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/qemu/hw/char/
H A Dtrace-events40 escc_soft_reset_chn(char channel) "soft reset channel %c"
41 escc_put_queue(char channel, int b) "channel %c put: 0x%02x"
42 escc_get_queue(char channel, int val) "channel %c get 0x%02x"
44 escc_update_parameters(char channel, int speed, int parity, int data_bits, int stop_bits) "channel …
45 escc_mem_writeb_ctrl(char channel, uint32_t reg, uint32_t val) "Write channel %c, reg[%d] = 0x%2.2x"
46 escc_mem_writeb_data(char channel, uint32_t val) "Write channel %c, ch %d"
47 escc_mem_readb_ctrl(char channel, uint32_t reg, uint8_t val) "Read channel %c, reg[%d] = 0x%2.2x"
48 escc_mem_readb_data(char channel, uint32_t ret) "Read channel %c, ch %d"
49 escc_serial_receive_byte(char channel, int ch) "channel %c put ch %d"
89 exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
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H A Dipoctal232.c193 static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val) in write_cr() argument
195 SCC2698Channel *ch = &dev->ch[channel]; in write_cr()
196 SCC2698Block *blk = &dev->blk[channel / 2]; in write_cr()
198 DPRINTF("Write CR%c %u: ", channel + 'a', val); in write_cr()
212 blk->isr |= ISR_TXRDY(channel); in write_cr()
217 blk->isr &= ~ISR_TXRDY(channel); in write_cr()
236 blk->isr &= ~ISR_RXRDY(channel); in write_cr()
241 blk->isr &= ~ISR_TXRDY(channel); in write_cr()
263 addr[7:5]: channel (a-h) in io_read()
266 unsigned channel = addr >> 4; in io_read() local
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H A Dexynos4210_uart.c161 uint32_t channel; member
220 static uint32_t exynos4210_uart_FIFO_trigger_level(uint32_t channel, in exynos4210_uart_FIFO_trigger_level() argument
225 switch (channel) { in exynos4210_uart_FIFO_trigger_level()
239 trace_exynos_uart_channel_error(channel); in exynos4210_uart_FIFO_trigger_level()
253 return exynos4210_uart_FIFO_trigger_level(s->channel, reg); in exynos4210_uart_Tx_FIFO_trigger_level()
264 return exynos4210_uart_FIFO_trigger_level(s->channel, reg); in exynos4210_uart_Rx_FIFO_trigger_level()
278 trace_exynos_uart_dmabusy(s->channel); in exynos4210_uart_update_dmabusy()
281 trace_exynos_uart_dmaready(s->channel); in exynos4210_uart_update_dmabusy()
319 trace_exynos_uart_irq_raised(s->channel, s->reg[I_(UINTP)]); in exynos4210_uart_update_irq()
322 trace_exynos_uart_irq_lowered(s->channel); in exynos4210_uart_update_irq()
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/qemu/include/io/
H A Dchannel-tls.h24 #include "io/channel.h"
29 #define TYPE_QIO_CHANNEL_TLS "qio-channel-tls"
36 * The QIOChannelTLS class provides a channel wrapper which
39 * technical restriction on which type of master channel is
42 * This channel object is capable of running as either a
57 * @ioc: the TLS channel object
68 * @master: the underlying channel object
73 * Create a new TLS channel that runs the server side of
80 * After creating the channel, it is mandatory to call
82 * todo any I/O on the channel.
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H A Dchannel.h28 #define TYPE_QIO_CHANNEL "qio-channel"
67 * The QIOChannel defines the core API for a generic I/O channel
100 * must follow to provide specific channel implementations.
173 * @ioc: the channel object
176 * Determine whether the channel implementation supports
186 * @ioc: the channel object
189 * Add channel support for the feature named in @feature.
196 * @ioc: the channel object
197 * @name: the name of the channel
199 * Sets the name of the channel, which serves as an aid
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H A Dchannel-websock.h24 #include "io/channel.h"
29 #define TYPE_QIO_CHANNEL_WEBSOCK "qio-channel-websock"
42 * The QIOChannelWebsock class provides a channel wrapper which
45 * technical restriction on which type of master channel is
48 * This channel object is currently only capable of running as
72 * @master: the underlying channel object
74 * Create a new websockets channel that runs the server
77 * After creating the channel, it is mandatory to call
79 * todo any I/O on the channel.
82 * via the new websocket channel object and not the original
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H A Dchannel-socket.h24 #include "io/channel.h"
29 #define TYPE_QIO_CHANNEL_SOCKET "qio-channel-socket"
36 * The QIOChannelSocket class provides a channel implementation
38 * Beyond the core channel API, it also provides functionality
58 * Create a channel for performing I/O on a socket
63 * Returns: the socket channel object
73 * Create a channel for performing I/O on the socket
76 * Returns: the socket channel object, or NULL on error
85 * @ioc: the socket channel object
100 * @ioc: the socket channel object
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H A Dchannel-file.h24 #include "io/channel.h"
27 #define TYPE_QIO_CHANNEL_FILE "qio-channel-file"
34 * The QIOChannelFile object provides a channel implementation
54 * Create a new IO channel object for a file represented
61 * The channel will own the passed in file descriptor
64 * should dup() its FD before opening the channel.
66 * Returns: the new channel object
76 * Create a new IO channel object for a file represented by the @fd
80 * The channel will own the duplicated file descriptor and will take
84 * Returns: the new channel object
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/qemu/hw/dma/
H A Dxlnx_dpdma.c298 uint8_t channel) in xlnx_dpdma_descriptor_start_address() argument
300 return (s->registers[DPDMA_DSCR_STRT_ADDRE_CH(channel)] << 16) in xlnx_dpdma_descriptor_start_address()
301 + s->registers[DPDMA_DSCR_STRT_ADDR_CH(channel)]; in xlnx_dpdma_descriptor_start_address()
305 uint8_t channel) in xlnx_dpdma_descriptor_next_address() argument
307 return ((uint64_t)s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] << 32) in xlnx_dpdma_descriptor_next_address()
308 + s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)]; in xlnx_dpdma_descriptor_next_address()
312 uint8_t channel) in xlnx_dpdma_is_channel_enabled() argument
314 return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_EN) != 0; in xlnx_dpdma_is_channel_enabled()
318 uint8_t channel) in xlnx_dpdma_is_channel_paused() argument
320 return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_PAUSED) != 0; in xlnx_dpdma_is_channel_paused()
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/qemu/io/
H A Dmeson.build3 'channel-buffer.c',
4 'channel-command.c',
5 'channel-file.c',
6 'channel-null.c',
7 'channel-socket.c',
8 'channel-tls.c',
9 'channel-util.c',
10 'channel-watch.c',
11 'channel-websock.c',
12 'channel.c',
/qemu/include/hw/xen/interface/
H A Devent_channel.h41 * @cmd == EVTCHNOP_* (event-channel operation).
85 * EVTCHNOP_bind_interdomain: Construct an interdomain event channel between
91 * In case the peer domain has already tried to set our event channel
93 * the local event channel pending.
96 * handler) is as follows: (Re-enable the event channel for subsequent
114 * EVTCHNOP_bind_virq: Bind a local event channel to VIRQ <irq> on specified
121 * 3. Per-vcpu VIRQs may be bound to at most one event channel per vcpu.
122 * The allocated event channel is bound to the specified vcpu and the
135 * EVTCHNOP_bind_pirq: Bind a local event channel to a real IRQ (PIRQ <irq>).
137 * 1. A physical IRQ may be bound to at most one event channel per domain.
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/qemu/hw/xen/
H A Dxen-bus.c842 XenEventChannel *channel = opaque; in xen_device_poll() local
844 return channel->handler(channel->opaque); in xen_device_poll()
849 XenEventChannel *channel = opaque; in xen_device_event() local
850 unsigned long port = qemu_xen_evtchn_pending(channel->xeh); in xen_device_event()
852 if (port == channel->local_port) { in xen_device_event()
853 xen_device_poll(channel); in xen_device_event()
855 qemu_xen_evtchn_unmask(channel->xeh, port); in xen_device_event()
860 XenEventChannel *channel, in xen_device_set_event_channel_context() argument
864 if (!channel) { in xen_device_set_event_channel_context()
865 error_setg(errp, "bad channel"); in xen_device_set_event_channel_context()
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/qemu/migration/
H A Dchannel.c2 * QEMU live migration channel operations
14 #include "channel.h"
20 #include "io/channel-tls.h"
21 #include "io/channel-socket.h"
26 * @migration_channel_process_incoming - Create new incoming migration channel
31 * @ioc: Channel to which we are connecting
60 * @migration_channel_connect - Create new outgoing migration channel
63 * @ioc: Channel to which we are connecting
103 * @migration_channel_read_peek - Peek at migration channel, without
104 * actually removing it from channel buffer.
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H A Dmultifd.h33 * channel.
185 /* channel number */
187 /* channel thread name */
189 /* channel thread id */
194 /* communication channel */
229 /* packets sent through this channel */
243 /* channel number */
245 /* channel thread name */
247 /* channel thread id */
250 /* communication channel */
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H A Dcpr-transfer.c10 #include "io/channel-file.h"
11 #include "io/channel-socket.h"
20 QEMUFile *cpr_transfer_output(MigrationChannel *channel, Error **errp) in cpr_transfer_output() argument
22 MigrationAddress *addr = channel->addr; in cpr_transfer_output()
39 error_setg(errp, "bad cpr channel address; must be unix"); in cpr_transfer_output()
44 QEMUFile *cpr_transfer_input(MigrationChannel *channel, Error **errp) in cpr_transfer_input() argument
46 MigrationAddress *addr = channel->addr; in cpr_transfer_input()
71 error_setg(errp, "bad cpr channel socket type; must be unix"); in cpr_transfer_input()
H A Dmigration.h23 #include "io/channel.h"
24 #include "io/channel-buffer.h"
131 * Number of postcopy channels including the default precopy channel, so
132 * vanilla postcopy will only contain one channel which contain both
144 * One can wait on this semaphore to wait until the preempt channel is
159 * fast channel.
162 * because it needs to continuously read data from the channel, and
165 * release the broken channel.
170 * channel.
236 * thread finished loading its data before the preempt channel has
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/qemu/docs/system/s390x/
H A Dcss.rst1 The virtual channel subsystem
4 QEMU implements a virtual channel subsystem with subchannels, (mostly
5 functionless) channel paths, and channel devices (virtio-ccw, 3270, and
7 multiple channel subsystems extended (MCSS-E).
9 All channel devices support the ``devno`` property, which takes a parameter
12 The default channel subsystem image id (``<cssid>``) is ``0xfe``. Devices in
13 there will show up in channel subsystem image ``0`` to guests that do not
69 * a virtio-mouse device in a non-standard channel subsystem image::
78 * a virtio-keyboard device in another non-standard channel subsystem image::
83 the standard channel subsystem image id.
/qemu/docs/devel/migration/
H A DCPR.rst160 option for the main migration channel, like normal live migration.
161 In addition, the user adds a second -incoming option with channel
162 type ``cpr``. This CPR channel must support file descriptor transfer
166 adding a second migration channel of type ``cpr`` in the channels
171 New QEMU reads the CPR channel before opening a monitor, hence
172 the CPR channel cannot be specified in the list of channels for a
188 * Issue the ``migrate`` command, containing a main channel and
189 a cpr channel.
204 The main incoming migration channel address cannot be a file type.
206 If the main incoming channel address is an inet socket, then the port
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/qemu/qga/
H A Dchannel-posix.c6 #include "channel.h"
25 static gboolean ga_channel_listen_accept(GIOChannel *channel, in ga_channel_listen_accept() argument
32 g_assert(channel != NULL); in ga_channel_listen_accept()
34 client_fd = qemu_accept(g_io_channel_unix_get_fd(channel), NULL, NULL); in ga_channel_listen_accept()
86 static gboolean ga_channel_client_event(GIOChannel *channel, in ga_channel_client_event() argument
113 g_warning("error setting channel encoding to binary"); in ga_channel_client_add()
141 error_setg_errno(errp, errno, "error opening channel '%s'", path); in ga_channel_open()
147 error_setg_errno(errp, errno, "error setting event mask for channel"); in ga_channel_open()
154 * In the default state channel sends echo of every command to a in ga_channel_open()
160 error_setg_errno(errp, errno, "error getting channel termios attrs"); in ga_channel_open()
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/qemu/tests/unit/
H A Dtest-io-channel-file.c2 * QEMU I/O channel file test
22 #include "io/channel-file.h"
23 #include "io/channel-util.h"
24 #include "io-channel-helpers.h"
28 #define TEST_FILE "tests/test-io-channel-file.txt"
147 g_test_add_func("/io/channel/file", test_io_channel_file); in main()
148 g_test_add_func("/io/channel/file/rdwr", test_io_channel_file_rdwr); in main()
149 g_test_add_func("/io/channel/file/fd", test_io_channel_fd); in main()
151 g_test_add_func("/io/channel/pipe/sync", test_io_channel_pipe_sync); in main()
152 g_test_add_func("/io/channel/pipe/async", test_io_channel_pipe_async); in main()
H A Dtest-io-channel-command.c2 * QEMU I/O channel command test
25 #include "io/channel-command.h"
26 #include "io-channel-helpers.h"
30 #define TEST_FIFO "test-io-channel-command.fifo"
37 g_autofree gchar *tmpdir = g_dir_make_tmp("qemu-test-io-channel.XXXXXX", NULL); in test_io_channel_command_fifo()
136 g_test_add_func("/io/channel/command/fifo/sync", in main()
138 g_test_add_func("/io/channel/command/fifo/async", in main()
141 g_test_add_func("/io/channel/command/echo/sync", in main()
143 g_test_add_func("/io/channel/command/echo/async", in main()
H A Dtest-io-channel-tls.c2 * QEMU I/O channel TLS test
27 #include "io/channel-tls.h"
28 #include "io/channel-socket.h"
29 #include "io-channel-helpers.h"
37 #define WORKDIR "tests/test-io-channel-tls-work/"
117 int channel[2]; in test_io_channel_tls() local
124 g_assert(qemu_socketpair(AF_UNIX, SOCK_STREAM, 0, channel) == 0); in test_io_channel_tls()
126 #define CLIENT_CERT_DIR "tests/test-io-channel-tls-client/" in test_io_channel_tls()
127 #define SERVER_CERT_DIR "tests/test-io-channel-tls-server/" in test_io_channel_tls()
176 channel[0], &error_abort); in test_io_channel_tls()
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/qemu/include/hw/dma/
H A Dxlnx_dpdma.h50 * xlnx_dpdma_start_operation: Start the operation on the specified channel. The
59 * @channel The channel to start.
61 size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, uint8_t channel,
67 * channel.
70 * @channel The channel associated to the pointer.
74 void xlnx_dpdma_set_host_data_location(XlnxDPDMAState *s, uint8_t channel,
/qemu/hw/misc/
H A Dbcm2835_cprman.c16 * channels. Those channel are then connected to the clock muxes. Each mux has
23 * At each level (PLL, channel and mux), the clock can be altered through
30 * /-->[PLL]-|->[PLL channel]--... [mux]--> to peripherals
31 * | |->[PLL channel] muxes takes [mux]
32 * | \->[PLL channel] inputs from [mux]
34 * [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux]
35 * | \->[PLL channel] ...-->[mux]
37 * \-->[PLL]--->[PLL channel] [mux]
153 /* PLL channel */
163 static bool pll_channel_is_enabled(CprmanPllChannelState *channel) in pll_channel_is_enabled() argument
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