Lines Matching full:channel
298 uint8_t channel) in xlnx_dpdma_descriptor_start_address() argument
300 return (s->registers[DPDMA_DSCR_STRT_ADDRE_CH(channel)] << 16) in xlnx_dpdma_descriptor_start_address()
301 + s->registers[DPDMA_DSCR_STRT_ADDR_CH(channel)]; in xlnx_dpdma_descriptor_start_address()
305 uint8_t channel) in xlnx_dpdma_descriptor_next_address() argument
307 return ((uint64_t)s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] << 32) in xlnx_dpdma_descriptor_next_address()
308 + s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)]; in xlnx_dpdma_descriptor_next_address()
312 uint8_t channel) in xlnx_dpdma_is_channel_enabled() argument
314 return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_EN) != 0; in xlnx_dpdma_is_channel_enabled()
318 uint8_t channel) in xlnx_dpdma_is_channel_paused() argument
320 return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_PAUSED) != 0; in xlnx_dpdma_is_channel_paused()
324 uint8_t channel) in xlnx_dpdma_is_channel_retriggered() argument
328 & DPDMA_GBL_RTRG_CH(channel); in xlnx_dpdma_is_channel_retriggered()
329 s->registers[DPDMA_GBL] &= ~DPDMA_GBL_RTRG_CH(channel); in xlnx_dpdma_is_channel_retriggered()
334 uint8_t channel) in xlnx_dpdma_is_channel_triggered() argument
336 return s->registers[DPDMA_GBL] & DPDMA_GBL_TRG_CH(channel); in xlnx_dpdma_is_channel_triggered()
339 static void xlnx_dpdma_update_desc_info(XlnxDPDMAState *s, uint8_t channel, in xlnx_dpdma_update_desc_info() argument
342 s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] = in xlnx_dpdma_update_desc_info()
344 s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)] = desc->next_descriptor; in xlnx_dpdma_update_desc_info()
345 s->registers[DPDMA_PYLD_CUR_ADDRE_CH(channel)] = in xlnx_dpdma_update_desc_info()
347 s->registers[DPDMA_PYLD_CUR_ADDR_CH(channel)] = desc->source_address; in xlnx_dpdma_update_desc_info()
348 s->registers[DPDMA_VDO_CH(channel)] = in xlnx_dpdma_update_desc_info()
352 s->registers[DPDMA_PYLD_SZ_CH(channel)] = desc->xfer_size; in xlnx_dpdma_update_desc_info()
353 s->registers[DPDMA_DSCR_ID_CH(channel)] = desc->descriptor_id; in xlnx_dpdma_update_desc_info()
356 s->registers[DPDMA_STATUS_CH(channel)] = in xlnx_dpdma_update_desc_info()
359 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_DSCR_INTR; in xlnx_dpdma_update_desc_info()
362 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_DSCR_UP; in xlnx_dpdma_update_desc_info()
365 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_DSCR_DONE; in xlnx_dpdma_update_desc_info()
368 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_IGNR_DONE; in xlnx_dpdma_update_desc_info()
371 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_LDSCR_FRAME; in xlnx_dpdma_update_desc_info()
374 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_LAST_DSCR; in xlnx_dpdma_update_desc_info()
377 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_CRC; in xlnx_dpdma_update_desc_info()
380 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_MODE; in xlnx_dpdma_update_desc_info()
383 s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_BURST_TYPE; in xlnx_dpdma_update_desc_info()
503 * We store the value anyway so we can know if the channel is in xlnx_dpdma_write()
676 size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, uint8_t channel, in xlnx_dpdma_start_operation() argument
685 assert(channel <= 5); in xlnx_dpdma_start_operation()
687 DPRINTF("start dpdma channel 0x%" PRIX8 "\n", channel); in xlnx_dpdma_start_operation()
689 if (!xlnx_dpdma_is_channel_triggered(s, channel)) { in xlnx_dpdma_start_operation()
690 DPRINTF("Channel isn't triggered..\n"); in xlnx_dpdma_start_operation()
694 if (!xlnx_dpdma_is_channel_enabled(s, channel)) { in xlnx_dpdma_start_operation()
695 DPRINTF("Channel isn't enabled..\n"); in xlnx_dpdma_start_operation()
699 if (xlnx_dpdma_is_channel_paused(s, channel)) { in xlnx_dpdma_start_operation()
700 DPRINTF("Channel is paused..\n"); in xlnx_dpdma_start_operation()
705 if ((s->operation_finished[channel]) in xlnx_dpdma_start_operation()
706 || xlnx_dpdma_is_channel_retriggered(s, channel)) { in xlnx_dpdma_start_operation()
707 desc_addr = xlnx_dpdma_descriptor_start_address(s, channel); in xlnx_dpdma_start_operation()
708 s->operation_finished[channel] = false; in xlnx_dpdma_start_operation()
710 desc_addr = xlnx_dpdma_descriptor_next_address(s, channel); in xlnx_dpdma_start_operation()
714 s->registers[DPDMA_EISR] |= ((1 << 1) << channel); in xlnx_dpdma_start_operation()
716 s->operation_finished[channel] = true; in xlnx_dpdma_start_operation()
721 xlnx_dpdma_update_desc_info(s, channel, &desc); in xlnx_dpdma_start_operation()
729 s->registers[DPDMA_EISR] |= ((1 << 7) << channel); in xlnx_dpdma_start_operation()
731 s->operation_finished[channel] = true; in xlnx_dpdma_start_operation()
738 s->registers[DPDMA_EISR] |= ((1 << 13) << channel); in xlnx_dpdma_start_operation()
740 s->operation_finished[channel] = true; in xlnx_dpdma_start_operation()
748 s->registers[DPDMA_EISR] |= ((1 << 25) << channel); in xlnx_dpdma_start_operation()
750 s->operation_finished[channel] = true; in xlnx_dpdma_start_operation()
758 s->operation_finished[channel] = done; in xlnx_dpdma_start_operation()
759 if (s->data[channel]) { in xlnx_dpdma_start_operation()
768 &s->data[channel][ptr], in xlnx_dpdma_start_operation()
771 s->registers[DPDMA_ISR] |= ((1 << 12) << channel); in xlnx_dpdma_start_operation()
797 &(s->data[channel][ptr]), in xlnx_dpdma_start_operation()
800 s->registers[DPDMA_ISR] |= ((1 << 12) << channel); in xlnx_dpdma_start_operation()
824 s->registers[DPDMA_ISR] |= (1 << channel); in xlnx_dpdma_start_operation()
833 void xlnx_dpdma_set_host_data_location(XlnxDPDMAState *s, uint8_t channel, in xlnx_dpdma_set_host_data_location() argument
842 assert(channel <= 5); in xlnx_dpdma_set_host_data_location()
843 s->data[channel] = p; in xlnx_dpdma_set_host_data_location()