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/kvm-unit-tests/x86/
H A Dsyscall.c12 u16 cs = read_cs(), ss = read_ss(); in test_syscall_lazy_load() local
17 wrmsr(MSR_STAR, (uint64_t)cs << 32); in test_syscall_lazy_load()
28 * This uses 32-bit syscall/sysret because KVM emulates it on Intel processors.
29 * However, the same bug happens with 64-bit syscall/sysret if two vCPUs
36 code_segment_upon_db = regs->cs; in handle_db()
37 regs->rflags &= ~(1 << 8); in handle_db()
42 " cmpl $0, code_segment_upon_db(%rip)\n"
47 /* 32-bit, ring-3 part of test_syscall_tf */
75 * syscall to syscall32_target -> TF cleared and no singlestep in test_syscall_tf()
88 rax = (ulong)&tss[0].rsp0; in test_syscall_tf()
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H A Dtaskswitch2.c3 #include "apic-defs.h"
11 #define MAIN_TSS_SEL (FIRST_SPARE_SEL + 0)
68 if (*error_code == 0x2) /* write access, not present */ in do_pf_tss()
71 fault_phys | PT_PRESENT_MASK | PT_WRITABLE_MASK, 0); in do_pf_tss()
91 asm volatile ("ljmp $" xstr(TSS_MAIN) ", $0"); in jmp_tss()
122 test_count = 0; in test_kernel_mode_int()
130 test_count = 0; in test_kernel_mode_int()
133 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, 0); in test_kernel_mode_int()
139 test_count = 0; in test_kernel_mode_int()
141 set_intr_task_gate(0xf0, irq_tss); in test_kernel_mode_int()
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H A Dsvm.h63 VMCB_CLEAN_SEG = 256, /* CS, DS, SS, ES, CPL */
111 #define TLB_CONTROL_DO_NOTHING 0
114 #define V_TPR_MASK 0x0f
126 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
154 #define SVM_VM_CR_VALID_MASK 0x001fULL
155 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
156 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
158 #define TSC_RATIO_DEFAULT 0x0100000000ULL
169 struct vmcb_seg cs; member
218 #define SVM_CPUID_FUNC 0x8000000a
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H A Dsvm_tests.c16 #define SVM_EXIT_MAX_DR_INTERCEPT 0x3f
46 return vmcb->control.exit_code == SVM_EXIT_VMMCALL; in null_check()
51 vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMRUN); in prepare_no_vmrun_int()
56 return vmcb->control.exit_code == SVM_EXIT_ERR; in check_no_vmrun_int()
61 asm volatile ("vmrun %0" : : "a"(virt_to_phys(vmcb))); in test_vmrun()
66 return vmcb->control.exit_code == SVM_EXIT_VMRUN; in check_vmrun()
72 vmcb->control.intercept |= 1 << INTERCEPT_RSM; in prepare_rsm_intercept()
73 vmcb->control.intercept_exceptions |= (1ULL << UD_VECTOR); in prepare_rsm_intercept()
89 case 0: in finished_rsm_intercept()
90 if (vmcb->control.exit_code != SVM_EXIT_RSM) { in finished_rsm_intercept()
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H A Dsvm.c109 return test->scratch; in get_test_stage()
115 test->scratch = s; in set_test_stage()
122 test->scratch++; in inc_test_stage()
129 seg->selector = selector; in vmcb_set_seg()
130 seg->attrib = attr; in vmcb_set_seg()
131 seg->limit = limit; in vmcb_set_seg()
132 seg->base = base; in vmcb_set_seg()
162 struct vmcb_save_area *save = &vmcb->save; in vmcb_ident()
163 struct vmcb_control_area *ctrl = &vmcb->control; in vmcb_ident()
170 memset(vmcb, 0, sizeof(*vmcb)); in vmcb_ident()
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H A Deventinj.c7 #include "apic-defs.h"
24 APIC_INT_ASSERT | v, 0); in apic_self_ipi()
29 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, 0); in apic_self_nmi()
34 outl(__s, 0xe4); \
35 } while (0)
40 } while (0)
61 stack_phys | PT_PRESENT_MASK | PT_WRITABLE_MASK, 0); in do_pf_tss()
69 // no task on x86_64, save/restore caller-save regs
94 printf("NP isr running %lx err=%lx\n", r->rip, r->error_code); in np_isr()
113 printf("Nested NMI isr running rip=%lx\n", r->rip); in nested_nmi_isr()
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H A Drealmode.c7 #define ARRAY_SIZE(_a) (sizeof(_a)/sizeof((_a)[0]))
17 #define NULL ((void*)0)
25 "mov $0x1234, %eax \n\t"
33 for (n = 0; *str; ++str) in strlen()
40 asm volatile("out %0, %1" : : "a"(data), "d"(port)); in outb()
44 static int serial_iobase = 0x3f8;
45 static int serial_inited = 0;
50 asm volatile("in %1, %0" : "=a"(data) : "d"(port)); in inb()
59 lsr = inb(serial_iobase + 0x05); in serial_outb()
60 } while (!(lsr & 0x20)); in serial_outb()
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H A Demulator64.c1 #define MAGIC_NUM 0xdeadbeefdeadbeefUL
2 #define GS_BASE 0x400000
20 unsigned long memw = 0x123456789abcdeful; in test_push()
22 memset(mem, 0x55, (void *)stack_top - mem); in test_push()
26 "pushq $-7 \n\t" in test_push()
29 "pushq $-7070707 \n\t" in test_push()
34 [reg]"r"(-17l), [mem]"r"(&memw) in test_push()
37 report(stack_top[-1] == -7ul, "push $imm8"); in test_push()
38 report(stack_top[-2] == -17ul, "push %%reg"); in test_push()
39 report(stack_top[-3] == 0x123456789abcdeful, "push mem"); in test_push()
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H A Dvmx_tests.c51 int pos = -1; in ffs()
53 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" in ffs()
93 "mov %%rsp, %0\n\t" in vmenter_main()
99 : "g"(0xABCD)); in vmenter_main()
100 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); in vmenter_main()
109 if (regs.rax != 0xABCD) { in vmenter_exit_handler()
113 regs.rax = 0xFFFF; in vmenter_exit_handler()
137 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; in preemption_timer_init()
149 vmx_set_test_stage(0); in preemption_timer_main()
156 if (((rdtsc() - tsc_val) >> preempt_scale) in preemption_timer_main()
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/kvm-unit-tests/lib/x86/
H A Disr.c71 set_idt_entry(vec, thunk, 0); in handle_irq()
75 *thunk++ = 0x48; *thunk++ = 0x83; *thunk++ = 0xec; *thunk++ = 0x08; in handle_irq()
77 *thunk++ = 0xc7; *thunk++ = 0x04; *thunk++ = 0x24; in handle_irq()
80 *thunk++ = 0xc7; *thunk++ = 0x44; *thunk++ = 0x24; *thunk++ = 0x04; in handle_irq()
83 *thunk ++ = 0xe9; in handle_irq()
84 *(u32 *)thunk = (ulong)isr_entry_point - (ulong)(thunk + 4); in handle_irq()
87 *thunk++ = 0x68; in handle_irq()
90 *thunk++ = 0xe9; in handle_irq()
91 *(u32 *)thunk = (ulong)isr_entry_point - (ulong)(thunk + 4); in handle_irq()
99 idt->offset0 | ((unsigned long)idt->offset1 << 16); in handle_external_interrupt()
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H A Ddesc.c6 #include "apic-defs.h"
8 /* Boot-related data structures */
11 idt_entry_t boot_idt[256] = {0};
14 .limit = sizeof(boot_idt) - 1,
21 { 0, 0, 0, .type_limit_flags = 0x0000}, /* 0x00 null */
22 {0xffff, 0, 0, .type_limit_flags = 0xcf9b}, /* flat 32-bit code segment */
23 {0xffff, 0, 0, .type_limit_flags = 0xcf93}, /* flat 32-bit data segment */
24 {0xffff, 0, 0, .type_limit_flags = 0xcf1b}, /* flat 32-bit code segment, not present */
25 { 0, 0, 0, .type_limit_flags = 0x0000}, /* TSS for task gates */
26 {0xffff, 0, 0, .type_limit_flags = 0x8f9b}, /* 16-bit code segment */
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H A Dsmp.c15 #define IPI_VECTOR 0x20
50 apic_write(APIC_EOI, 0); in ipi()
56 apic_write(APIC_EOI, 0); in ipi()
107 ipi_done = 0; in __on_cpu()
125 __on_cpu(cpu, function, data, 0); in on_cpu_async()
132 for (cpu = cpu_count() - 1; cpu >= 0; --cpu) in on_cpus()
150 set_idt_entry(IPI_VECTOR, ipi_entry, 0); in smp_init()
152 setup_smp_id(0); in smp_init()
154 on_cpu(i, setup_smp_id, 0); in smp_init()
170 on_cpu(i, do_reset_apic, 0); in smp_reset_apic()
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H A Ddesc.h5 * selector 32-bit 64-bit
6 * 0x00 NULL descriptor NULL descriptor
7 * 0x08 ring-0 code segment (32-bit) ring-0 code segment (64-bit)
8 * 0x10 ring-0 data segment (32-bit) ring-0 data segment (32/64-bit)
9 * 0x18 ring-0 code segment (P=0) ring-0 code segment (64-bit, P=0)
10 * 0x20 intr_alt_stack TSS ring-0 code segment (32-bit)
11 * 0x28 ring-0 code segment (16-bit) same
12 * 0x30 ring-0 data segment (16-bit) same
13 * 0x38 (0x3b) ring-3 code segment (32-bit) same
14 * 0x40 (0x43) ring-3 data segment (32-bit) ring-3 data segment (32/64-bit)
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H A Dusermode.c3 #include "x86/apic-defs.h"
14 #define USERMODE_STACK_SIZE 0x2000
15 #define RET_TO_KERNEL_IRQ 0x20
27 regs->rip = (unsigned long)&restore_exec_to_jmpbuf; in restore_exec_to_jmpbuf_exception_handler()
28 regs->cs = KERNEL_CS; in restore_exec_to_jmpbuf_exception_handler()
30 regs->ss = KERNEL_DS; in restore_exec_to_jmpbuf_exception_handler()
39 volatile uint64_t rax = 0; in run_in_user()
43 *raised_vector = 0; in run_in_user()
48 if (setjmp(jmpbuf) != 0) { in run_in_user()
51 return 0; in run_in_user()
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H A Dprocessor.h11 #define CANONICAL_48_VAL 0xffffaaaaaaaaaaaaull
12 #define CANONICAL_57_VAL 0xffaaaaaaaaaaaaaaull
13 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull
19 * Get a linear address by combining @addr with a non-canonical pattern in the
37 #define DE_VECTOR 0
62 #define X86_CR0_PE_BIT (0)
85 #define X86_CR3_PCID_MASK GENMASK(11, 0)
91 #define X86_CR4_VME_BIT (0)
143 #define X86_EFLAGS_CF_BIT (0)
149 /* RESERVED 0 (3) */
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/kvm-unit-tests/arm/
H A Dmicro-bench.c9 * unittest.cfg for micro-bench, allowing a client program to get the
15 * Author: Shih-Wei Li <shihwei@cs.columbia.edu>
16 * Author: Christoffer Dall <cdall@cs.columbia.edu>
24 #include <asm/gic-v3-its.h>
27 #define QEMU_MMIO_ADDR 0x0a000008
102 while (!irq_ready && tries--) in gic_prep_common()
124 nr_ipi_received = 0; in ipi_prep()
148 nr_ipi_received = 0; in ipi_hw_prep()
161 while (!irq_received && tries--) in ipi_exec()
196 static int received = 0; in lpi_exec()
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