Lines Matching +full:cs +full:- +full:0
11 #define CANONICAL_48_VAL 0xffffaaaaaaaaaaaaull
12 #define CANONICAL_57_VAL 0xffaaaaaaaaaaaaaaull
13 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull
19 * Get a linear address by combining @addr with a non-canonical pattern in the
37 #define DE_VECTOR 0
62 #define X86_CR0_PE_BIT (0)
85 #define X86_CR3_PCID_MASK GENMASK(11, 0)
91 #define X86_CR4_VME_BIT (0)
143 #define X86_EFLAGS_CF_BIT (0)
149 /* RESERVED 0 (3) */
152 /* RESERVED 0 (5) */
168 /* RESERVED 0 (15) */
204 : "0"(function), "2"(index)); in raw_cpuid()
210 u32 level = raw_cpuid(function & 0xf0000000, 0).a; in cpuid_indexed()
212 return (struct cpuid) { 0, 0, 0, 0 }; in cpuid_indexed()
218 return cpuid_indexed(function, 0); in cpuid()
223 struct cpuid c = cpuid(0); in is_intel()
226 return strcmp((char *)name, "GenuineIntel") == 0; in is_intel()
230 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be
249 static_assert((fn & 0xc0000000) == 0 || \
250 (fn & 0xc0000000) == 0x40000000 || \
251 (fn & 0xc0000000) == 0x80000000 || \
252 (fn & 0xc0000000) == 0xc0000000); \
260 #define X86_FEATURE_MWAIT X86_CPU_FEATURE(0x1, 0, ECX, 3)
261 #define X86_FEATURE_VMX X86_CPU_FEATURE(0x1, 0, ECX, 5)
262 #define X86_FEATURE_PDCM X86_CPU_FEATURE(0x1, 0, ECX, 15)
263 #define X86_FEATURE_PCID X86_CPU_FEATURE(0x1, 0, ECX, 17)
264 #define X86_FEATURE_X2APIC X86_CPU_FEATURE(0x1, 0, ECX, 21)
265 #define X86_FEATURE_MOVBE X86_CPU_FEATURE(0x1, 0, ECX, 22)
266 #define X86_FEATURE_TSC_DEADLINE_TIMER X86_CPU_FEATURE(0x1, 0, ECX, 24)
267 #define X86_FEATURE_XSAVE X86_CPU_FEATURE(0x1, 0, ECX, 26)
268 #define X86_FEATURE_OSXSAVE X86_CPU_FEATURE(0x1, 0, ECX, 27)
269 #define X86_FEATURE_RDRAND X86_CPU_FEATURE(0x1, 0, ECX, 30)
270 #define X86_FEATURE_MCE X86_CPU_FEATURE(0x1, 0, EDX, 7)
271 #define X86_FEATURE_APIC X86_CPU_FEATURE(0x1, 0, EDX, 9)
272 #define X86_FEATURE_CLFLUSH X86_CPU_FEATURE(0x1, 0, EDX, 19)
273 #define X86_FEATURE_DS X86_CPU_FEATURE(0x1, 0, EDX, 21)
274 #define X86_FEATURE_XMM X86_CPU_FEATURE(0x1, 0, EDX, 25)
275 #define X86_FEATURE_XMM2 X86_CPU_FEATURE(0x1, 0, EDX, 26)
276 #define X86_FEATURE_TSC_ADJUST X86_CPU_FEATURE(0x7, 0, EBX, 1)
277 #define X86_FEATURE_HLE X86_CPU_FEATURE(0x7, 0, EBX, 4)
278 #define X86_FEATURE_SMEP X86_CPU_FEATURE(0x7, 0, EBX, 7)
279 #define X86_FEATURE_INVPCID X86_CPU_FEATURE(0x7, 0, EBX, 10)
280 #define X86_FEATURE_RTM X86_CPU_FEATURE(0x7, 0, EBX, 11)
281 #define X86_FEATURE_SMAP X86_CPU_FEATURE(0x7, 0, EBX, 20)
282 #define X86_FEATURE_PCOMMIT X86_CPU_FEATURE(0x7, 0, EBX, 22)
283 #define X86_FEATURE_CLFLUSHOPT X86_CPU_FEATURE(0x7, 0, EBX, 23)
284 #define X86_FEATURE_CLWB X86_CPU_FEATURE(0x7, 0, EBX, 24)
285 #define X86_FEATURE_INTEL_PT X86_CPU_FEATURE(0x7, 0, EBX, 25)
286 #define X86_FEATURE_UMIP X86_CPU_FEATURE(0x7, 0, ECX, 2)
287 #define X86_FEATURE_PKU X86_CPU_FEATURE(0x7, 0, ECX, 3)
288 #define X86_FEATURE_LA57 X86_CPU_FEATURE(0x7, 0, ECX, 16)
289 #define X86_FEATURE_RDPID X86_CPU_FEATURE(0x7, 0, ECX, 22)
290 #define X86_FEATURE_SHSTK X86_CPU_FEATURE(0x7, 0, ECX, 7)
291 #define X86_FEATURE_PKS X86_CPU_FEATURE(0x7, 0, ECX, 31)
292 #define X86_FEATURE_IBT X86_CPU_FEATURE(0x7, 0, EDX, 20)
293 #define X86_FEATURE_SPEC_CTRL X86_CPU_FEATURE(0x7, 0, EDX, 26)
294 #define X86_FEATURE_STIBP X86_CPU_FEATURE(0x7, 0, EDX, 27)
295 #define X86_FEATURE_FLUSH_L1D X86_CPU_FEATURE(0x7, 0, EDX, 28)
296 #define X86_FEATURE_ARCH_CAPABILITIES X86_CPU_FEATURE(0x7, 0, EDX, 29)
297 #define X86_FEATURE_SSBD X86_CPU_FEATURE(0x7, 0, EDX, 31)
298 #define X86_FEATURE_LAM X86_CPU_FEATURE(0x7, 1, EAX, 26)
303 #define KVM_FEATURE_ASYNC_PF X86_CPU_FEATURE(0x40000001, 0, EAX, 4)
304 #define KVM_FEATURE_ASYNC_PF_INT X86_CPU_FEATURE(0x40000001, 0, EAX, 14)
309 #define X86_FEATURE_SVM X86_CPU_FEATURE(0x80000001, 0, ECX, 2)
310 #define X86_FEATURE_PERFCTR_CORE X86_CPU_FEATURE(0x80000001, 0, ECX, 23)
311 #define X86_FEATURE_NX X86_CPU_FEATURE(0x80000001, 0, EDX, 20)
312 #define X86_FEATURE_GBPAGES X86_CPU_FEATURE(0x80000001, 0, EDX, 26)
313 #define X86_FEATURE_RDTSCP X86_CPU_FEATURE(0x80000001, 0, EDX, 27)
314 #define X86_FEATURE_LM X86_CPU_FEATURE(0x80000001, 0, EDX, 29)
315 #define X86_FEATURE_RDPRU X86_CPU_FEATURE(0x80000008, 0, EBX, 4)
316 #define X86_FEATURE_AMD_IBPB X86_CPU_FEATURE(0x80000008, 0, EBX, 12)
317 #define X86_FEATURE_AMD_IBRS X86_CPU_FEATURE(0x80000008, 0, EBX, 14)
318 #define X86_FEATURE_AMD_STIBP X86_CPU_FEATURE(0x80000008, 0, EBX, 15)
319 #define X86_FEATURE_AMD_STIBP_ALWAYS_ON X86_CPU_FEATURE(0x80000008, 0, EBX, 17)
320 #define X86_FEATURE_AMD_IBRS_SAME_MODE X86_CPU_FEATURE(0x80000008, 0, EBX, 19)
321 #define X86_FEATURE_AMD_SSBD X86_CPU_FEATURE(0x80000008, 0, EBX, 24)
322 #define X86_FEATURE_NPT X86_CPU_FEATURE(0x8000000A, 0, EDX, 0)
323 #define X86_FEATURE_LBRV X86_CPU_FEATURE(0x8000000A, 0, EDX, 1)
324 #define X86_FEATURE_NRIPS X86_CPU_FEATURE(0x8000000A, 0, EDX, 3)
325 #define X86_FEATURE_TSCRATEMSR X86_CPU_FEATURE(0x8000000A, 0, EDX, 4)
326 #define X86_FEATURE_PAUSEFILTER X86_CPU_FEATURE(0x8000000A, 0, EDX, 10)
327 #define X86_FEATURE_PFTHRESHOLD X86_CPU_FEATURE(0x8000000A, 0, EDX, 12)
328 #define X86_FEATURE_VGIF X86_CPU_FEATURE(0x8000000A, 0, EDX, 16)
329 #define X86_FEATURE_VNMI X86_CPU_FEATURE(0x8000000A, 0, EDX, 25)
330 #define X86_FEATURE_SME X86_CPU_FEATURE(0x8000001F, 0, EAX, 0)
331 #define X86_FEATURE_SEV X86_CPU_FEATURE(0x8000001F, 0, EAX, 1)
332 #define X86_FEATURE_VM_PAGE_FLUSH X86_CPU_FEATURE(0x8000001F, 0, EAX, 2)
333 #define X86_FEATURE_SEV_ES X86_CPU_FEATURE(0x8000001F, 0, EAX, 3)
334 #define X86_FEATURE_SEV_SNP X86_CPU_FEATURE(0x8000001F, 0, EAX, 4)
335 #define X86_FEATURE_V_TSC_AUX X86_CPU_FEATURE(0x8000001F, 0, EAX, 9)
336 #define X86_FEATURE_SME_COHERENT X86_CPU_FEATURE(0x8000001F, 0, EAX, 10)
337 #define X86_FEATURE_DEBUG_SWAP X86_CPU_FEATURE(0x8000001F, 0, EAX, 14)
338 #define X86_FEATURE_SVSM X86_CPU_FEATURE(0x8000001F, 0, EAX, 28)
339 #define X86_FEATURE_SBPB X86_CPU_FEATURE(0x80000021, 0, EAX, 27)
340 #define X86_FEATURE_AMD_PMU_V2 X86_CPU_FEATURE(0x80000022, 0, EAX, 0)
343 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit
344 * value/property as opposed to a single-bit feature. Again, pack the info
345 * into a 64-bit value to pass by value with no overhead on 64-bit builds.
365 static_assert((fn & 0xc0000000) == 0 || \
366 (fn & 0xc0000000) == 0x40000000 || \
367 (fn & 0xc0000000) == 0x80000000 || \
368 (fn & 0xc0000000) == 0xc0000000); \
373 #define X86_PROPERTY_MAX_BASIC_LEAF X86_CPU_PROPERTY(0, 0, EAX, 0, 31)
374 #define X86_PROPERTY_PMU_VERSION X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7)
375 #define X86_PROPERTY_PMU_NR_GP_COUNTERS X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15)
376 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23)
377 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31)
378 #define X86_PROPERTY_PMU_EVENTS_MASK X86_CPU_PROPERTY(0xa, 0, EBX, 0, 7)
379 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31)
380 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4)
381 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12)
383 #define X86_PROPERTY_SUPPORTED_XCR0_LO X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31)
384 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31)
385 #define X86_PROPERTY_XSTATE_MAX_SIZE X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31)
386 #define X86_PROPERTY_SUPPORTED_XCR0_HI X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31)
388 #define X86_PROPERTY_XSTATE_TILE_SIZE X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31)
389 #define X86_PROPERTY_XSTATE_TILE_OFFSET X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31)
391 #define X86_PROPERTY_INTEL_PT_NR_RANGES X86_CPU_PROPERTY(0x14, 1, EAX, 0, 2)
393 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31)
394 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15)
395 #define X86_PROPERTY_AMX_BYTES_PER_TILE X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31)
396 #define X86_PROPERTY_AMX_BYTES_PER_ROW X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15)
397 #define X86_PROPERTY_AMX_NR_TILE_REGS X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31)
398 #define X86_PROPERTY_AMX_MAX_ROWS X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15)
400 #define X86_PROPERTY_MAX_KVM_LEAF X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31)
402 #define X86_PROPERTY_MAX_EXT_LEAF X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31)
403 #define X86_PROPERTY_MAX_PHY_ADDR X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7)
404 #define X86_PROPERTY_MAX_VIRT_ADDR X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15)
405 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23)
406 #define X86_PROPERTY_SEV_C_BIT X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5)
407 #define X86_PROPERTY_PHYS_ADDR_REDUCTION X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11)
408 #define X86_PROPERTY_NR_PERFCTR_CORE X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3)
409 #define X86_PROPERTY_NR_PERFCTR_NB X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15)
411 #define X86_PROPERTY_MAX_CENTAUR_LEAF X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31)
441 switch (property.function & 0xc0000000) { in this_cpu_has_p()
442 case 0: in this_cpu_has_p()
445 case 0x40000000: in this_cpu_has_p()
448 case 0x80000000: in this_cpu_has_p()
451 case 0xc0000000: in this_cpu_has_p()
468 return 0; in this_cpu_supported_xcr0()
486 asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory"); in clac()
491 asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory"); in stac()
498 asm volatile ("mov %%cs, %0" : "=mr"(val)); in read_cs()
506 asm volatile ("mov %%ds, %0" : "=mr"(val)); in read_ds()
514 asm volatile ("mov %%es, %0" : "=mr"(val)); in read_es()
522 asm volatile ("mov %%ss, %0" : "=mr"(val)); in read_ss()
530 asm volatile ("mov %%fs, %0" : "=mr"(val)); in read_fs()
538 asm volatile ("mov %%gs, %0" : "=mr"(val)); in read_gs()
545 asm volatile ("pushf; pop %0\n\t" : "=rm"(f)); in read_rflags()
551 asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory"); in write_ds()
556 asm volatile ("mov %0, %%es" : : "rm"(val) : "memory"); in write_es()
561 asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory"); in write_ss()
566 asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory"); in write_fs()
571 asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory"); in write_gs()
576 asm volatile ("push %0; popf\n\t" : : "rm"(f)); in write_rflags()
588 * infrastructure uses per-CPU data and thus consumes GS.base. Various tests
613 *(val) = 0; \
669 return rdreg64_safe(".byte 0x0f,0x01,0xd0", index, result); in xgetbv_safe()
674 return wrreg64_safe(".byte 0x0f,0x01,0xd1", index, value); in xsetbv_safe()
679 return asm_safe("mov %0,%%cr0", "r" (val)); in write_cr0_safe()
693 asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory"); in read_cr0()
699 asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory"); in write_cr2()
705 asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory"); in read_cr2()
711 return asm_safe("mov %0,%%cr3", "r" (val)); in write_cr3_safe()
725 asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory"); in read_cr3()
736 return asm_safe("mov %0,%%cr4", "r" (val)); in write_cr4_safe()
750 asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory"); in read_cr4()
756 asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory"); in write_cr8()
762 asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory"); in read_cr8()
768 asm volatile ("lgdt %0" : : "m"(*ptr)); in lgdt()
773 return asm_safe("lgdt %0", "m"(*ptr)); in lgdt_safe()
778 return asm_fep_safe("lgdt %0", "m"(*ptr)); in lgdt_fep_safe()
783 asm volatile ("sgdt %0" : "=m"(*ptr)); in sgdt()
788 asm volatile ("lidt %0" : : "m"(*ptr)); in lidt()
793 return asm_safe("lidt %0", "m"(*ptr)); in lidt_safe()
798 return asm_fep_safe("lidt %0", "m"(*ptr)); in lidt_fep_safe()
803 asm volatile ("sidt %0" : "=m"(*ptr)); in sidt()
808 asm volatile ("lldt %0" : : "rm"(val)); in lldt()
813 return asm_safe("lldt %0", "rm"(val)); in lldt_safe()
818 return asm_safe("lldt %0", "rm"(val)); in lldt_fep_safe()
824 asm volatile ("sldt %0" : "=rm"(val)); in sldt()
830 asm volatile ("ltr %0" : : "rm"(val)); in ltr()
835 return asm_safe("ltr %0", "rm"(val)); in ltr_safe()
840 return asm_safe("ltr %0", "rm"(val)); in ltr_fep_safe()
846 asm volatile ("str %0" : "=rm"(val)); in str()
852 asm volatile ("mov %0, %%dr0" : : "r"(val) : "memory"); in write_dr0()
857 asm volatile ("mov %0, %%dr1" : : "r"(val) : "memory"); in write_dr1()
862 asm volatile ("mov %0, %%dr2" : : "r"(val) : "memory"); in write_dr2()
867 asm volatile ("mov %0, %%dr3" : : "r"(val) : "memory"); in write_dr3()
872 asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory"); in write_dr6()
878 asm volatile ("mov %%dr6, %0" : "=r"(val)); in read_dr6()
884 asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory"); in write_dr7()
890 asm volatile ("mov %%dr7, %0" : "=r"(val)); in read_dr7()
934 asm volatile("rdrand %0\n\t" in rdrand()
936 "mov $0, %0\n\t" in rdrand()
1002 asm volatile("invlpg (%0)" ::"r" (va) : "memory"); in invlpg()
1014 return asm_safe(".byte 0x66,0x0f,0x38,0x82,0x18", "a" (desc), "b" (type)); in invpcid_safe()
1021 * instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may
1032 unsigned int ecx = 0; in read_pkru()
1035 asm volatile(".byte 0x0f,0x01,0xee\n\t" in read_pkru()
1045 unsigned int ecx = 0; in write_pkru()
1046 unsigned int edx = 0; in write_pkru()
1048 asm volatile(".byte 0x0f,0x01,0xef\n\t" in write_pkru()
1061 shift_amt = 64 - va_width; in is_canonical()
1076 *(volatile u64 *)NONCANONICAL = 0; in generate_non_canonical_gp()
1108 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. in generate_usermode_ac()
1110 * on a 16-byte boundary as x86_64 stacks should be. in generate_usermode_ac()
1112 asm volatile("movq $0, -0x4(%rsp)"); in generate_usermode_ac()
1114 return 0; in generate_usermode_ac()
1118 * Switch from 64-bit to 32-bit mode and generate #OF via INTO. Note, if RIP
1119 * or RSP holds a 64-bit value, this helper will NOT generate #OF.
1129 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); in generate_of()
1140 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); in generate_of()
1144 "movl $0x7fffffff, %eax;" in generate_of()