Lines Matching +full:cs +full:- +full:0

3 #include "apic-defs.h"
11 #define MAIN_TSS_SEL (FIRST_SPARE_SEL + 0)
68 if (*error_code == 0x2) /* write access, not present */ in do_pf_tss()
71 fault_phys | PT_PRESENT_MASK | PT_WRITABLE_MASK, 0); in do_pf_tss()
91 asm volatile ("ljmp $" xstr(TSS_MAIN) ", $0"); in jmp_tss()
122 test_count = 0; in test_kernel_mode_int()
130 test_count = 0; in test_kernel_mode_int()
133 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, 0); in test_kernel_mode_int()
139 test_count = 0; in test_kernel_mode_int()
141 set_intr_task_gate(0xf0, irq_tss); in test_kernel_mode_int()
143 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | APIC_INT_ASSERT | 0xf0, 0); in test_kernel_mode_int()
150 set_intr_task_gate(0, de_tss); in test_kernel_mode_int()
151 printf("Try to divide by 0\n"); in test_kernel_mode_int()
153 : "d"(0), "a"(1500), "m"(test_divider)); in test_kernel_mode_int()
157 /* test if call HW exception DE by int $0 triggers task gate */ in test_kernel_mode_int()
158 test_count = 0; in test_kernel_mode_int()
159 set_intr_task_gate(0, de_tss); in test_kernel_mode_int()
160 printf("Call int 0\n"); in test_kernel_mode_int()
161 asm volatile ("int $0"); in test_kernel_mode_int()
162 printf("Return from int 0\n"); in test_kernel_mode_int()
163 report(test_count == 1, "int $0"); in test_kernel_mode_int()
166 test_count = 0; in test_kernel_mode_int()
174 test_count = 0; in test_kernel_mode_int()
187 test_count = 0; in test_kernel_mode_int()
190 *fault_addr = 0; in test_kernel_mode_int()
198 test_count = 0; in test_gdt_task_gate()
201 /* hlt opcode is 0xf4 I use destination IP 0xf4f4f4f4 to catch in test_gdt_task_gate()
203 asm volatile("lcall $" xstr(TSS_INTR) ", $0xf4f4f4f4"); in test_gdt_task_gate()
208 test_count = 0; in test_gdt_task_gate()
209 asm volatile("lcall $" xstr(TSS_INTR) ", $0xf4f4f4f4"); in test_gdt_task_gate()
213 test_count = 0; in test_gdt_task_gate()
216 asm volatile ("ljmp $" xstr(TSS_INTR) ", $0xf4f4f4f4"); in test_gdt_task_gate()
229 vm86_start = (void*) 0x42000; in test_vm86_switch()
230 vm86_start[0] = 0x0f; in test_vm86_switch()
231 vm86_start[1] = 0x0b; in test_vm86_switch()
234 set_gdt_entry(MAIN_TSS_SEL, (u32)&main_tss, sizeof(tss32_t) - 1, 0x89, 0); in test_vm86_switch()
242 set_gdt_entry(VM86_TSS_SEL, (u32)&vm86_tss, sizeof(tss32_t) - 1, 0x8b, 0); in test_vm86_switch()
244 .eflags = 0x20002, in test_vm86_switch()
246 .eip = (u32) vm86_start & 0x0f, in test_vm86_switch()
247 .cs = (u32) vm86_start >> 4, in test_vm86_switch()
248 .ds = 0x1234, in test_vm86_switch()
249 .es = 0x2345, in test_vm86_switch()
259 "orw $0x4000, (%esp)\n" in test_vm86_switch()
270 /* test lcall with conforming segment, cs.dpl != cs.rpl */ in test_conforming_switch()
271 test_count = 0; in test_conforming_switch()
273 tss_intr.cs = CONFORM_CS_SEL | 3; in test_conforming_switch()
278 set_gdt_entry(CONFORM_CS_SEL, 0, 0xffffffff, 0x9f, 0xc0); in test_conforming_switch()
279 asm volatile("lcall $" xstr(TSS_INTR) ", $0xf4f4f4f4"); in test_conforming_switch()
280 report(test_count == 1, "lcall with cs.rpl != cs.dpl"); in test_conforming_switch()