Merge branch 'arm/queue' into 'master'

arm/arm64: PMU test fixes and a micro-bench improvement

See merge request kvm-unit-tests/kvm-unit-tests!49

arm64: microbench: Improve measurement accuracy of tests

Reducing the impact of the cntvct_el0 register and isb() operation
on microbenchmark test results to improve testing accuracy and reduce
late

arm64: microbench: Improve measurement accuracy of tests

Reducing the impact of the cntvct_el0 register and isb() operation
on microbenchmark test results to improve testing accuracy and reduce
latency in test results.

Signed-off-by: heqiong <heqiong1557@phytium.com.cn>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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Merge branch 'arm/queue' into 'master'

arm64: microbench: Benchmark with virtual instead of physical timer

See merge request kvm-unit-tests/kvm-unit-tests!47

arm64: microbench: Benchmark with virtual instead of physical timer

Use the virtual instead of the physical timer for measuring the time
taken to execute the microbenchmark.

Internal testing discov

arm64: microbench: Benchmark with virtual instead of physical timer

Use the virtual instead of the physical timer for measuring the time
taken to execute the microbenchmark.

Internal testing discovered a performance regression on this test
starting with Linux commit 680232a94c12 "KVM: arm64: timers: Allow
save/restoring of the physical timer". Oliver Upton speculates QEMU is
changing the guest physical counter to have a nonzero offset since it
gained the ability as of that commit. As a consequence KVM is
trap-and-emulating here on architectures without FEAT_ECV.

While this isn't a correctness issue, the trap-and-emulate overhead of
physical counter emulation on systems without ECV leads to surprising
microbenchmark results.

Signed-off-by: Colton Lewis <coltonlewis@google.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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Merge branch 'arm/queue' into 'master'

arm/arm64: EFI support, arm64 backtrace support, PMU test improvements, and more

See merge request kvm-unit-tests/kvm-unit-tests!43

arm64: Add support for timer initialization through ACPI

For systems with ACPI support, we can discover timers through the ACPI
GTDT table. This change implements the code to discover timers through

arm64: Add support for timer initialization through ACPI

For systems with ACPI support, we can discover timers through the ACPI
GTDT table. This change implements the code to discover timers through
the GTDT and adds ACPI support in timer_save_state. This change
retains the default behavior; we check if a valid DT is provided, if
not, we try to discover timers using ACPI.

Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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Merge branch 'arm/queue' into 'master'

arm cleanups

See merge request kvm-unit-tests/kvm-unit-tests!41

arm64: microbench: Use gic_enable_irq() macro in microbench test

Use gic_enable_irq() to clean up code.

Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat

arm64: microbench: Use gic_enable_irq() macro in microbench test

Use gic_enable_irq() to clean up code.

Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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Merge branch 'arm/queue' into 'master'

arm/queue: configure and run script improvements

See merge request kvm-unit-tests/kvm-unit-tests!27

arm: Fix typos

Correct typos which were discovered with the "codespell" utility.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

arm64: Add mmio_addr arg to arm/micro-bench

Add a command line arg to arm/micro-bench to set the mmio_addr to other
values besides the default QEMU one. Default to the QEMU value if no arg
is passed

arm64: Add mmio_addr arg to arm/micro-bench

Add a command line arg to arm/micro-bench to set the mmio_addr to other
values besides the default QEMU one. Default to the QEMU value if no arg
is passed.

Signed-off-by: Ricardo Koller <ricarkol@google.com>
Message-Id: <20211008174022.3028983-1-ricarkol@google.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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Merge branch 'arm/queue' into 'master'

arm/arm64: target-efi prep

This series mostly prepares kvm-unit-tests/arm for targeting EFI
platforms. The actually EFI support will come in another series,
b

Merge branch 'arm/queue' into 'master'

arm/arm64: target-efi prep

This series mostly prepares kvm-unit-tests/arm for targeting EFI
platforms. The actually EFI support will come in another series,
but these patches are good for removing assumptions from our memory
maps and about our PSCI conduit, even if we never merge EFI support.

See merge request kvm-unit-tests/kvm-unit-tests!8

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arm64: micro-bench: ioremap userspace_emulated_addr

We should explicitly ioremap the userspace emulated address used
in the benchmark.

Reported-by: Alexandru Elisei <alexandru.elisei@arm.com>
Revie

arm64: micro-bench: ioremap userspace_emulated_addr

We should explicitly ioremap the userspace emulated address used
in the benchmark.

Reported-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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Merge branch 'arm/queue' into 'master'

arm/arm64: Fixes, improvements, and prep for target-efi

See merge request kvm-unit-tests/kvm-unit-tests!6

arm64: microbench: fix unexpected PPI

For the origin value of CNTV_CVAL_EL0 architecturally UNKNOWN, we may
receive an unexpected PPI before we actual trigger the timer interrupt.
So we should set A

arm64: microbench: fix unexpected PPI

For the origin value of CNTV_CVAL_EL0 architecturally UNKNOWN, we may
receive an unexpected PPI before we actual trigger the timer interrupt.
So we should set ARCH_TIMER_CTL_IMASK in timer_prep.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

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arm64: microbench: Add timer_post() to get actual PPI latency

For we get the time duration of (10msec timer + injection latency)
in timer_exec(), we substract the value of 10msec in timer_post()
to

arm64: microbench: Add timer_post() to get actual PPI latency

For we get the time duration of (10msec timer + injection latency)
in timer_exec(), we substract the value of 10msec in timer_post()
to get the actual latency.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
[ Adapt to the modified post() interface. ]
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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arm64: microbench: Add test->post() to further process test results

Under certain circumstances, we need to further process microbench
test results, so we add test->post() in the microbench framewor

arm64: microbench: Add test->post() to further process test results

Under certain circumstances, we need to further process microbench
test results, so we add test->post() in the microbench framework,
later patch will use that.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
[ Drop total_ns from post() input arguments. ]
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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arm64: microbench: Add vtimer latency test

Trigger PPIs by setting up a 10msec timer and test the latency.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
[ Replaced GICv3 assumption in timer_

arm64: microbench: Add vtimer latency test

Trigger PPIs by setting up a 10msec timer and test the latency.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
[ Replaced GICv3 assumption in timer_prep() with switch on gic_version() ]
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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arm64: microbench: Add time limit for each individual test

Besides using separate running times parameter, we add time limit
for loop_test to make sure each test should be done in a certain
time(5 s

arm64: microbench: Add time limit for each individual test

Besides using separate running times parameter, we add time limit
for loop_test to make sure each test should be done in a certain
time(5 sec here).

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
[ Initialize total_ns to zero. ]
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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arm64: microbench: Allow each test to specify its running times

For some test in micro-bench can be time consuming, we add a
micro-bench test parameter to allow each individual test to specify
its r

arm64: microbench: Allow each test to specify its running times

For some test in micro-bench can be time consuming, we add a
micro-bench test parameter to allow each individual test to specify
its running times.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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arm64: microbench: its: Add LPI latency test

Triggers LPIs through the INT command and test the latency.
Mostly inherited form commit 0ef02cd6cbaa(arm/arm64: ITS: INT
functional tests).

Signed-off-

arm64: microbench: its: Add LPI latency test

Triggers LPIs through the INT command and test the latency.
Mostly inherited form commit 0ef02cd6cbaa(arm/arm64: ITS: INT
functional tests).

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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arm64: microbench: gic: Add ipi latency test for gicv4.1 support kvm

If gicv4.1(sgi hardware injection) is supported in kvm, we test ipi
injection via hw/sw way separately.

Signed-off-by: Jingyi Wa

arm64: microbench: gic: Add ipi latency test for gicv4.1 support kvm

If gicv4.1(sgi hardware injection) is supported in kvm, we test ipi
injection via hw/sw way separately.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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arm64: microbench: Generalize ipi test names

Later patches will use these functions for gic(ipi/lpi/timer) tests.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
Reviewed-by: Eric Auger <eric.

arm64: microbench: Generalize ipi test names

Later patches will use these functions for gic(ipi/lpi/timer) tests.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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arm64: microbench: get correct ipi received num

If ipi_exec() fails because of timeout, we shouldn't increase
the number of ipi received.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
Review

arm64: microbench: get correct ipi received num

If ipi_exec() fails because of timeout, we shouldn't increase
the number of ipi received.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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arm64: microbench: Add timer_post() to get actual PPI latency

For we get the time duration of (10msec timer + injection latency)
in timer_exec(), we substract the value of 10msec in timer_post()
to

arm64: microbench: Add timer_post() to get actual PPI latency

For we get the time duration of (10msec timer + injection latency)
in timer_exec(), we substract the value of 10msec in timer_post()
to get the actual latency.

Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
[ Adapt to the modified post() interface. ]
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...