/qemu/net/can/ |
H A D | can_core.c | 4 * Copyright (c) 2013-2014 Jin Yang 5 * Copyright (c) 2014-2018 Pavel Pisa 50 0, 1, 2, 3, 4, 5, 6, 7, 8, /* 0 - 8 */ 51 9, 9, 9, 9, /* 9 - 12 */ 52 10, 10, 10, 10, /* 13 - 16 */ 53 11, 11, 11, 11, /* 17 - 20 */ 54 12, 12, 12, 12, /* 21 - 24 */ 55 13, 13, 13, 13, 13, 13, 13, 13, /* 25 - 32 */ 56 14, 14, 14, 14, 14, 14, 14, 14, /* 33 - 40 */ 57 14, 14, 14, 14, 14, 14, 14, 14, /* 41 - 48 */ [all …]
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/qemu/include/hw/net/ |
H A D | mii.h | 8 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> 34 #define MII_CTRL1000 9 /* 1000BASE-T control */ 35 #define MII_STAT1000 10 /* 1000BASE-T status */ 37 #define MII_MDDAADR 14 /* MMD access address data */ 47 #define MII_BMCR_LOOPBACK (1 << 14) 52 #define MII_BMCR_ISOLATE (1 << 10) /* Isolate data paths from MII */ 59 #define MII_BMSR_100TX_FD (1 << 14) /* Can do 100mbps, full-duplex */ 60 #define MII_BMSR_100TX_HD (1 << 13) /* Can do 100mbps, half-duplex */ 61 #define MII_BMSR_10T_FD (1 << 12) /* Can do 10mbps, full-duplex */ 62 #define MII_BMSR_10T_HD (1 << 11) /* Can do 10mbps, half-duplex */ [all …]
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H A D | npcm_gmac.h | 46 #define RX_DESC_RDES0_FRAME_LEN_MASK(word) extract32(word, 16, 14) 52 #define RX_DESC_RDES0_DESC_ERR_MASK BIT(14) 60 #define RX_DESC_RDES0_VLAN_TAG_MASK BIT(10) 114 #define TX_DESC_TDES0_JBBR_TMT_MASK BIT(14) 122 #define TX_DESC_TDES0_NO_CARR_MASK BIT(10) 170 #define TYPE_NPCM_GMAC "npcm-gmac" 211 #define NPCM_DMA_STATUS_ERI BIT(14) 215 #define NPCM_DMA_STATUS_ETI BIT(10) 258 #define NPCM_DMA_INTR_ENAB_ERE BIT(14) 262 #define NPCM_DMA_INTR_ENAB_ETE BIT(10) [all …]
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/qemu/tests/tcg/aarch64/ |
H A D | fcvt.ref | 3 Converting single-precision to half-precision 4 00 SINGLE: -nan / 0xffa00000 (0 => OK) 6 01 SINGLE: -nan / 0xffc00000 (0 => OK) 8 02 SINGLE: -inf / 0xff800000 (0 => OK) 10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK) 12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK) 14 05 SINGLE: -1.11100003258488635273e+30 / 0xf1605d5b (0 => OK) 16 06 SINGLE: -1.08700982243137289629e-12 / 0xab98fba8 (0 => OK) 18 07 SINGLE: -1.78051176151664730511e-20 / 0x9ea82a22 (0 => OK) 20 08 SINGLE: -1.17549435082228750797e-38 / 0x80800000 (0 => OK) [all …]
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/qemu/tests/tcg/arm/ |
H A D | fcvt.ref | 3 Converting single-precision to half-precision 4 00 SINGLE: -nan / 0xffa00000 (0 => OK) 6 01 SINGLE: -nan / 0xffc00000 (0 => OK) 8 02 SINGLE: -inf / 0xff800000 (0 => OK) 10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK) 12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK) 14 05 SINGLE: -1.11100003258488635273e+30 / 0xf1605d5b (0 => OK) 16 06 SINGLE: -1.08700982243137289629e-12 / 0xab98fba8 (0 => OK) 18 07 SINGLE: -1.78051176151664730511e-20 / 0x9ea82a22 (0 => OK) 20 08 SINGLE: -1.17549435082228750797e-38 / 0x80800000 (0 => OK) [all …]
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/qemu/gdb-xml/ |
H A D | i386-32bit.xml | 2 <!-- Copyright (C) 2010-2017 Free Software Foundation, Inc. 6 notice and this notice are preserved. --> 8 <!-- I386 with SSE --> 10 <!DOCTYPE target SYSTEM "gdb-target.dtd"> 21 <field name="NT" start="14" end="14"/> 24 <field name="DF" start="10" end="10"/> 56 <!-- Segment descriptor caches and TLS base MSRs --> 58 <!--reg name="cs_base" bitsize="32" type="int32"/> 61 <reg name="es_base" bitsize="32" type="int32"/--> 82 <!--field name="" start="3" end="11"/> [all …]
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H A D | i386-64bit.xml | 2 <!-- Copyright (C) 2010-2017 Free Software Foundation, Inc. 6 notice and this notice are preserved. --> 8 <!-- x86_64 64bit --> 10 <!DOCTYPE target SYSTEM "gdb-target.dtd"> 22 <field name="NT" start="14" end="14"/> 25 <field name="DF" start="10" end="10"/> 38 <!-- General registers --> 60 <!-- Segment registers --> 69 <!-- Segment descriptor caches and TLS base MSRs --> 71 <!--reg name="cs_base" bitsize="64" type="int64"/> [all …]
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/qemu/include/hw/usb/ |
H A D | dwc2-regs.h | 1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ 7 * hw.h - DesignWare HS OTG Controller hardware definitions 9 * Copyright 2004-2013 Synopsys, Inc. 20 * 3. The names of the above-listed copyright holders may not be used 58 #define GOTGCTL_HSTSETHNPEN BIT(10) 109 #define GUSBCFG_USBTRDTIM_MASK (0xf << 10) 110 #define GUSBCFG_USBTRDTIM_SHIFT 10 158 #define GINTSTS_ISOUTDROP BIT(14) 162 #define GINTSTS_ERLYSUSP BIT(10) 251 #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14) [all …]
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/qemu/linux-user/hppa/ |
H A D | vdso.S | 6 * SPDX-License-Identifier: GPL-2.0-or-later 10 #include "vdso-asmoffset.h" 18 * a 64-byte boundary by 0, 4 or 5 instructions. Since the vdso trampoline 28 /* arch/parisc/kernel/asm-offsets.c */ 30 (offsetof_sigcontext - PARISC_RT_SIGFRAME_SIZE32) 54 .cfi_def_cfa 30, -PARISC_RT_SIGFRAME_SIZE32 + offsetof_sigcontext 66 .cfi_offset 10, offsetof_sigcontext_gr + 10 * 4 70 .cfi_offset 14, offsetof_sigcontext_gr + 14 * 4 102 .cfi_offset 44, offsetof_sigcontext_fr + 10 * 8 103 .cfi_offset 45, offsetof_sigcontext_fr + 10 * 8 + 4 [all …]
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/qemu/linux-user/ppc/ |
H A D | vdso.S | 6 * SPDX-License-Identifier: GPL-2.0-or-later 15 #include "vdso-asmoffset.h" 22 .size \name, .-\name 101 .cfi_offset 10, 10 * sizeof_reg 105 .cfi_offset 14, 14 * sizeof_reg 137 .cfi_offset 42, offsetof_mcontext_fregs + 10 * sizeof_freg 141 .cfi_offset 46, offsetof_mcontext_fregs + 14 * sizeof_freg 196 save_vreg 10 200 save_vreg 14 229 * The non-rt sigreturn has the same layout at a different offset.
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/qemu/tests/tcg/mips/ |
H A D | hello-mips.c | 4 * http://www.linux-mips.org/wiki/RISC/os 5 * http://www.linux-mips.org/wiki/MIPSABIHistory 6 * http://www.linux.com/howtos/Assembly-HOWTO/mips.shtml 8 * mipsel-linux-gcc -nostdlib -mno-abicalls -fno-PIC -fno-stack-protector \ 9 * -mabi=32 -O2 -static -o hello-mips hello-mips.c 28 : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", in exit1() 49 : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", in write() 56 return -1; in write() 62 write (1, "Hello, World!\n", 14); in __start()
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/qemu/target/mips/tcg/ |
H A D | mxu_translate.c | 4 * Copyright (c) 2004-2005 Jocelyn Mayer 10 * SPDX-License-Identifier: LGPL-2.1-or-later 32 * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is 41 * XRa, XRb, XRc, XRd - MXU registers 42 * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers 44 * Non-register operands: 46 * aptn1 - 1-bit accumulate add/subtract pattern 47 * aptn2 - 2-bit accumulate add/subtract pattern 48 * eptn2 - 2-bit execute add/subtract pattern 49 * optn2 - 2-bit operand pattern [all …]
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H A D | msa_helper.c | 24 #include "accel/tcg/cpu-ldst.h" 26 #include "exec/helper-proto.h" 35 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1) 36 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1) 38 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1))) 39 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1))) 41 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df))) 42 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m))) 46 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df))) 48 /* Element-by-element access macros */ [all …]
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/qemu/include/hw/misc/ |
H A D | aspeed_scu.h | 9 * the COPYING file in the top-level directory. 19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" 20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" 21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600" 22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700" 23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700" 24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030" 86 * arch/arm/mach-aspeed/include/mach/regs-scu.h 88 * Copyright (C) 2012-2020 ASPEED Technology Inc. 110 * 14:12 SD/SDIO divider selection [all …]
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/qemu/include/ |
H A D | elf.h | 4 /* 32-bit ELF base types. */ 11 /* 64-bit ELF base types. */ 47 #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ 48 #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ 49 #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ 50 #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ 51 #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ 81 #define EF_MIPS_MACH_SB1 0x008a0000 /* Broadcom SB-1 */ 89 #define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra RM9000 */ 95 #define MIPS_ABI_FP_UNKNOWN (-1) /* Unknown FP ABI (internal) */ [all …]
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/qemu/target/mips/ |
H A D | cpu.h | 4 #include "cpu-qom.h" 5 #include "exec/cpu-common.h" 6 #include "exec/cpu-defs.h" 7 #include "exec/cpu-interrupt.h" 11 #include "fpu/softfloat-types.h" 13 #include "mips-defs.h" 32 uint64_t d; /* binary double fixed-point */ 33 uint32_t w[2]; /* binary single fixed-point */ 34 /* FPU/MSA register mapping is not tested on big-endian hosts. */ 117 #define CP0MVPC0_PVPE 10 [all …]
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/qemu/linux-user/loongarch64/ |
H A D | vdso.S | 6 * SPDX-License-Identifier: GPL-2.0-or-later 11 #include "vdso-asmoffset.h" 19 .size \name, . - \name 67 .cfi_offset 10, B_GR + 10 * 8 71 .cfi_offset 14, B_GR + 14 * 8 101 .cfi_offset 42, B_FR + 10 * 8 105 .cfi_offset 46, B_FR + 14 * 8
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/qemu/target/arm/ |
H A D | syndrome.h | 2 * QEMU ARM CPU -- syndrome functions and types 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 111 * The exception is FP/SIMD access traps -- these report extra information 167 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) in syn_aa64_sysregtrap() 177 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) in syn_cp14_rt_trap() 178 | (crn << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp14_rt_trap() 187 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) in syn_cp15_rt_trap() 188 | (crn << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp15_rt_trap() 198 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp14_rrt_trap() 208 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp15_rrt_trap() [all …]
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/qemu/tests/qemu-iotests/ |
H A D | 077 | 54 echo "open -o driver=$IMGFMT,file.align=4k blkdebug::$TEST_IMG" 57 aio_write -P 10 0x200 0x200 66 aio_write -P 10 $((off + 0x200)) 0x200 68 aio_write -P 11 $((off + 0x400)) 0x200 79 aio_write -P 10 0x5000 0x200 81 aio_write -P 11 0x5200 0x200 82 aio_write -P 12 0x5400 0x200 83 aio_write -P 13 0x5600 0x200 84 aio_write -P 14 0x5800 0x200 85 aio_write -P 15 0x5a00 0x200 [all …]
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/qemu/tests/qtest/ |
H A D | virtio-iommu-test.c | 10 * option) any later version. See the COPYING file in the top-level directory. 15 #include "libqtest-single.h" 18 #include "libqos/virtio-iommu.h" 19 #include "hw/virtio/virtio-iommu.h" 29 QVirtioDevice *dev = v_iommu->vdev; in pci_config() 48 g_assert_cmpint(buffer->reserved[i], ==, 0); in read_tail_status() 50 return buffer->status; in read_tail_status() 54 * send_attach_detach - Send an attach/detach command to the device 62 QVirtioDevice *dev = v_iommu->vdev; in send_attach_detach() 63 QVirtQueue *vq = v_iommu->vq; in send_attach_detach() [all …]
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/qemu/tests/tcg/xtensa/ |
H A D | test_windowed.S | 31 set_vector window_overflow_\window, 10f 35 10: 63 overflow_test \shift, \window, %((\shift) - 1), \probe 86 set_vector window_underflow_\window, 10f 99 10: 110 movi a3, (XCHAL_NUM_AREGS - (\window)) / 4 123 assert bsi.l, a2, (XCHAL_NUM_AREGS - (\window)) / 4 138 reset_window %(1 | (1 << ((XCHAL_NUM_AREGS - \window) / 4))) 153 movi a3, (XCHAL_NUM_AREGS - (\window)) / 4 157 assert bsi.l, a2, (XCHAL_NUM_AREGS - (\window)) / 4 [all …]
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/qemu/hw/net/ |
H A D | vmxnet3.h | 14 * See the COPYING file in the top-level directory. 53 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved. 67 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 72 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com> 77 u64 TSOPktsTxOK; /* TSO pkts post-segmentation */ 92 /* the following counters are for pkts from the wire, i.e., pre-LRO */ 168 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 209 * Little Endian layout of bitfields - 215 * Big Endian layout of bitfields - 232 u32 msscof:14; /* MSS, checksum offset, flags */ [all …]
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/qemu/target/hexagon/ |
H A D | arch.c | 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 78 {14, 18, 21, 24}, 79 {14, 17, 20, 23}, 82 {12, 14, 17, 20}, 83 {11, 14, 16, 19}, 85 {10, 12, 15, 17}, 86 {10, 12, 14, 16}, 88 {9, 11, 12, 14}, 89 {8, 10, 12, 14}, 92 {7, 9, 10, 12}, [all …]
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/qemu/util/ |
H A D | uuid.c | 33 uuid->data[8] = (uuid->data[8] & 0x3f) | 0x80; in qemu_uuid_generate() 35 time_hi_and_version field to the 4-bit version number. in qemu_uuid_generate() 37 uuid->data[6] = (uuid->data[6] & 0xf) | 0x40; in qemu_uuid_generate() 53 const unsigned char *uu = &uuid->data[0]; in qemu_uuid_unparse() 56 uu[8], uu[9], uu[10], uu[11], uu[12], uu[13], uu[14], uu[15]); in qemu_uuid_unparse() 61 const unsigned char *uu = &uuid->data[0]; in qemu_uuid_unparse_strdup() 64 uu[7], uu[8], uu[9], uu[10], uu[11], uu[12], in qemu_uuid_unparse_strdup() 65 uu[13], uu[14], uu[15]); in qemu_uuid_unparse_strdup() 75 if (str[i] != '-') { in qemu_uuid_is_valid() 92 unsigned char *uu = &uuid->data[0]; in qemu_uuid_parse() [all …]
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/qemu/linux-user/riscv/ |
H A D | vdso.S | 2 * RISC-V linux replacement vdso. 6 * SPDX-License-Identifier: GPL-2.0-or-later 15 #include "vdso-asmoffset.h" 22 .size \name, . - \name 45 sw zero, 0(a1) /* tz->tz_minuteswest = 0 */ 46 sw zero, 4(a1) /* tz->tz_dsttime = 0 */ 47 1: addi sp, sp, -32 57 .cfi_adjust_cfa_offset -32 59 li a0, -EOVERFLOW 63 divu t2, t2, t3 /* nsec -> usec */ [all …]
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