Lines Matching +full:10 +full:- +full:14
1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
7 * hw.h - DesignWare HS OTG Controller hardware definitions
9 * Copyright 2004-2013 Synopsys, Inc.
20 * 3. The names of the above-listed copyright holders may not be used
58 #define GOTGCTL_HSTSETHNPEN BIT(10)
109 #define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
110 #define GUSBCFG_USBTRDTIM_SHIFT 10
158 #define GINTSTS_ISOUTDROP BIT(14)
162 #define GINTSTS_ERLYSUSP BIT(10)
251 #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
252 #define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
253 #define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
254 #define GHWCFG2_NUM_DEV_EP_SHIFT 10
288 #define GHWCFG3_BC_SUPPORT BIT(14)
292 #define GHWCFG3_OPTIONAL_FEATURES BIT(10)
315 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
316 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
322 #define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10)
370 #define GPWRDN_CONNECT_DET_MSK BIT(14)
374 #define GPWRDN_RST_DET_MSK BIT(10)
417 #define GREFCLK_REF_CLK_MODE BIT(14)
430 #define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
468 #define DCTL_CGOUTNAK BIT(10)
538 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
539 * bits[25..22] - should always be zero, this isn't a periodic endpoint
540 * bits[10..0] - MPS setting different for EP0
585 #define DXEPINT_NYETINTRPT BIT(14)
658 #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
659 #define PCGCTL_PRT_CLK_SEL_SHIFT 14
663 #define PCGCTL_ENBL_EXTND_HIBER BIT(10)
743 #define HPRT0_LNSTS_MASK (0x3 << 10)
744 #define HPRT0_LNSTS_SHIFT 10
775 #define HCSPLT_XACTPOS_MASK (0x3 << 14)
776 #define HCSPLT_XACTPOS_SHIFT 14
788 #define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
792 #define HCINTMSK_DATATGLERR BIT(10)
829 * struct dwc2_dma_desc - DMA descriptor structure,