target/mips/cpu.h

4 #include "cpu-qom.h"
5 #include "exec/cpu-common.h"
6 #include "exec/cpu-defs.h"
7 #include "exec/cpu-interrupt.h"
11 #include "fpu/softfloat-types.h"
13 #include "mips-defs.h"
32     uint64_t d;    /* binary double fixed-point */
33     uint32_t w[2]; /* binary single fixed-point */
34 /* FPU/MSA register mapping is not tested on big-endian hosts. */
117 #define CP0MVPC0_PVPE   10
123 #define CP0MVPC1_PCP2   10
143  *     ----------        ----------        ----------        ----------
156  *     ----------        ----------        ----------        ----------
168  *     Register 8        Register 9        Register 10       Register 11
169  *     ----------        ----------        -----------       -----------
181  *     Register 12       Register 13       Register 14       Register 15
182  *     -----------       -----------       -----------       -----------
195  *     -----------       -----------       -----------       -----------
208  *     -----------       -----------       -----------       -----------
221  *     -----------       -----------       -----------       -----------
234  *     -----------       -----------       -----------       -----------
256 #define CP0_REGISTER_10    10
260 #define CP0_REGISTER_14    14
343 /* CP0 Register 10 */
364 /* CP0 Register 14 */
466      * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[])
488 #define CP0TCSt_IXMT    10
517     target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
543 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
577 #define CP0VPEC1_NCP2   10
584 #define CP0VPEOpt_IWX6  14
588 #define CP0VPEOpt_IWX2  10
707 #define CP0SRSC0_SRS2   10
713 #define CP0SRSC1_SRS5   10
719 #define CP0SRSC2_SRS8   10
725 #define CP0SRSC3_SRS11  10
730 #define CP0SRSC4_SRS14  10
752  * CP0 Register 10
755 #define CP0EnHi_EHINV 10
820  * CP0 Register 14
843 #define CP0C0_AT   13    /* 14..13 */
844 #define CP0C0_AR   10    /* 12..10 */
864 #define CP0C1_DL   10    /* 12..10 */
897 #define CP0C3_ISA          14    /* 15..14 */
901 #define CP0C3_DSPP         10
919 #define CP0C4_MMUExtDef    14
941 #define CP0C5_CA2          14
944 #define CP0C5_L2C          10
967 #define CP0C6_VCLRU           14
971 #define CP0C6_UMEMUALEN       10
988     /* XXX: Maybe make LLAddr per-TC? */
1027 #define CP0DB_DEC  10
1118 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
1121 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
1124      * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
1129 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
1131 #define MIPS_HFLAG_M16_SHIFT 10
1146 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
1147 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
1256     return hflags_mmu_index(env->hflags);  in mips_env_mmu_index()
1261     EXCP_NONE          = -1,
1319 /* Check presence of MIPS-3D ASE */
1322     return env->active_fpu.fcr0 & (1 << FCR0_3D);  in ase_3d_available()
1328     return env->CP0_Config3 & (1 << CP0C3_MSAP);  in ase_msa_available()
1334     return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP);  in ase_lcsr_available()
1337 /* Check presence of multi-threading ASE implementation */
1340     return env->CP0_Config3 & (1 << CP0C3_MT);  in ase_mt_available()