Lines Matching +full:10 +full:- +full:14
4 * Copyright (c) 2004-2005 Jocelyn Mayer
10 * SPDX-License-Identifier: LGPL-2.1-or-later
32 * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
41 * XRa, XRb, XRc, XRd - MXU registers
42 * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
44 * Non-register operands:
46 * aptn1 - 1-bit accumulate add/subtract pattern
47 * aptn2 - 2-bit accumulate add/subtract pattern
48 * eptn2 - 2-bit execute add/subtract pattern
49 * optn2 - 2-bit operand pattern
50 * optn3 - 3-bit operand pattern
51 * sft4 - 4-bit shift amount
52 * strd2 - 2-bit stride amount
57 * S - single operation at a time 32 - word
58 * D - two operations in parallel 16 - half word
59 * Q - four operations in parallel 8 - byte
63 * ADD - Add or subtract
64 * ADDC - Add with carry-in
65 * ACC - Accumulate
66 * ASUM - Sum together then accumulate (add or subtract)
67 * ASUMC - Sum together then accumulate (add or subtract) with carry-in
68 * AVG - Average between 2 operands
69 * ABD - Absolute difference
70 * ALN - Align data
71 * AND - Logical bitwise 'and' operation
72 * CPS - Copy sign
73 * EXTR - Extract bits
74 * I2M - Move from GPR register to MXU register
75 * LDD - Load data from memory to XRF
76 * LDI - Load data from memory to XRF (and increase the address base)
77 * LUI - Load unsigned immediate
78 * MUL - Multiply
79 * MULU - Unsigned multiply
80 * MADD - 64-bit operand add 32x32 product
81 * MSUB - 64-bit operand subtract 32x32 product
82 * MAC - Multiply and accumulate (add or subtract)
83 * MAD - Multiply and add or subtract
84 * MAX - Maximum between 2 operands
85 * MIN - Minimum between 2 operands
86 * M2I - Move from MXU register to GPR register
87 * MOVZ - Move if zero
88 * MOVN - Move if non-zero
89 * NOR - Logical bitwise 'nor' operation
90 * OR - Logical bitwise 'or' operation
91 * STD - Store data from XRF to memory
92 * SDI - Store data from XRF to memory (and increase the address base)
93 * SLT - Set of less than comparison
94 * SAD - Sum of absolute differences
95 * SLL - Logical shift left
96 * SLR - Logical shift right
97 * SAR - Arithmetic shift right
98 * SAT - Saturation
99 * SFL - Shuffle
100 * SCOP - Calculate x’s scope (-1, means x<0; 0, means x==0; 1, means x>0)
101 * XOR - Logical bitwise 'exclusive or' operation
105 * E - Expand results
106 * F - Fixed point multiplication
107 * L - Low part result
108 * R - Doing rounding
109 * V - Variable instead of immediate
110 * W - Combine above L and V
117 * ----------------------- ---------------------------
141 * S8LDI XRa, Rb, s8, eptn3 -------------------------------------
151 * ----------------------- Q16ACCM XRa, XRb, XRc, XRd, eptn2
168 * Q8MOVN XRa, XRb, XRc ------------------
172 * -------------------- D32SAR XRa, XRb, XRc, XRd, sft4
181 * ------------------------- Q16SLLV XRa, XRb, Rb
187 * S32EXTR XRa, XRb, Rb, bits5 -----------------
205 * ├─ 000010 ─ <not assigned> (non-MXU OPC_MUL)
240 * ├─ 001111 ─ OPC_MXU_D16MACE 20 (13..10 don't care)
244 * │ 20 (13..10 don't care)
248 * │ 13..10
252 * │ 13..10
256 * │ 20 (13..10 don't care)
260 * │ 20 (13..10 don't care)
264 * │ 13..10
268 * │ 13..10
275 * │ └─ 10 ─ OPC_MXU_D32ASUM
280 * │ └─ 10 ─ OPC_MXU_D16ASUM
285 * ├─ 011101 ─ OPC_MXU_Q8ACCE └─ 10 ─ OPC_MXU_D8SUMC
291 * ├─ 100011 ─ OPC_MXU_S8STD 15..14
294 * │ ├─ 10 ─ OPC_MXU_S32EXTR
329 * │ └─ 10 ─ OPC_MXU_Q8MULSU
341 * │ └─ 10 ─ OPC_MXU_Q8MACSU
461 * MXU pool 04 05 06 07 08 09 10 11
487 * MXU pool 14
571 /* MXU accumulate add/subtract 1-bit pattern 'aptn1' */
575 /* MXU accumulate add/subtract 2-bit pattern 'aptn2' */
581 /* MXU execute add/subtract 2-bit pattern 'eptn2' */
609 static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
619 for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { in mxu_translate_init()
627 mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); in mxu_translate_init()
636 tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); in gen_load_mxu_gpr()
643 tcg_gen_mov_tl(mxu_gpr[reg - 1], t); in gen_store_mxu_gpr()
653 tcg_gen_extract_tl(t, mxu_gpr[reg - 1], ofs, len); in gen_extract_mxu_gpr()
670 * S32I2M XRa, rb - Register move from GRF to XRF
679 XRa = extract32(ctx->opcode, 6, 5); in gen_mxu_s32i2m()
680 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32i2m()
691 * S32M2I XRa, rb - Register move from XRF to GRF
700 XRa = extract32(ctx->opcode, 6, 5); in gen_mxu_s32m2i()
701 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32m2i()
713 * S8LDD XRa, Rb, s8, optn3 - Load a byte from memory to XRF
715 * S8LDI XRa, Rb, s8, optn3 - Load a byte from memory to XRF,
726 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s8ldd()
727 s8 = extract32(ctx->opcode, 10, 8); in gen_mxu_s8ldd()
728 optn3 = extract32(ctx->opcode, 18, 3); in gen_mxu_s8ldd()
729 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s8ldd()
740 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
746 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
752 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
758 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
764 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
769 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
775 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB); in gen_mxu_s8ldd()
783 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
793 * S8STD XRa, Rb, s8, optn3 - Store a byte from XRF to memory
795 * S8SDI XRa, Rb, s8, optn3 - Store a byte from XRF to memory,
806 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s8std()
807 s8 = extract32(ctx->opcode, 10, 8); in gen_mxu_s8std()
808 optn3 = extract32(ctx->opcode, 18, 3); in gen_mxu_s8std()
809 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s8std()
842 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8std()
846 * S16LDD XRa, Rb, s10, optn2 - Load a halfword from memory to XRF
848 * S16LDI XRa, Rb, s10, optn2 - Load a halfword from memory to XRF,
860 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s16ldd()
861 s10 = sextract32(ctx->opcode, 10, 9) * 2; in gen_mxu_s16ldd()
862 optn2 = extract32(ctx->opcode, 19, 2); in gen_mxu_s16ldd()
863 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s16ldd()
874 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UW); in gen_mxu_s16ldd()
880 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UW); in gen_mxu_s16ldd()
886 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SW); in gen_mxu_s16ldd()
890 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UW); in gen_mxu_s16ldd()
900 * S16STD XRa, Rb, s8, optn2 - Store a byte from XRF to memory
902 * S16SDI XRa, Rb, s8, optn2 - Store a byte from XRF to memory,
914 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s16std()
915 s10 = sextract32(ctx->opcode, 10, 9) * 2; in gen_mxu_s16std()
916 optn2 = extract32(ctx->opcode, 19, 2); in gen_mxu_s16std()
917 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s16std()
942 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_UW); in gen_mxu_s16std()
946 * S32MUL XRa, XRd, rs, rt - Signed 32x32=>64 bit multiplication
950 * S32MULU XRa, XRd, rs, rt - Unsigned 32x32=>64 bit multiplication
962 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32mul()
963 XRd = extract32(ctx->opcode, 10, 4); in gen_mxu_s32mul()
964 rs = extract32(ctx->opcode, 16, 5); in gen_mxu_s32mul()
965 rt = extract32(ctx->opcode, 21, 5); in gen_mxu_s32mul()
987 * D16MUL XRa, XRb, XRc, XRd, optn2 - Signed 16 bit pattern multiplication
988 * D16MULF XRa, XRb, XRc, optn2 - Signed Q15 fraction pattern multiplication
990 * D16MULE XRa, XRb, XRc, XRd, optn2 - Signed Q15 fraction pattern
1004 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16mul()
1005 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d16mul()
1006 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d16mul()
1007 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_d16mul()
1008 optn2 = extract32(ctx->opcode, 22, 2); in gen_mxu_d16mul()
1108 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16mac()
1109 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d16mac()
1110 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d16mac()
1111 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_d16mac()
1112 optn2 = extract32(ctx->opcode, 22, 2); in gen_mxu_d16mac()
1113 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_d16mac()
1216 * D16MADL XRa, XRb, XRc, XRd, aptn2, optn2 - Double packed
1229 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16madl()
1230 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d16madl()
1231 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d16madl()
1232 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_d16madl()
1233 optn2 = extract32(ctx->opcode, 22, 2); in gen_mxu_d16madl()
1234 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_d16madl()
1290 tcg_gen_or_tl(mxu_gpr[XRd - 1], t3, t2); in gen_mxu_d16madl()
1294 * S16MAD XRa, XRb, XRc, XRd, aptn2, optn2 - Single packed
1295 * signed 16 bit pattern multiply and 32-bit add/subtract.
1305 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s16mad()
1306 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_s16mad()
1307 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_s16mad()
1308 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_s16mad()
1309 optn2 = extract32(ctx->opcode, 22, 2); in gen_mxu_s16mad()
1310 aptn1 = extract32(ctx->opcode, 24, 1); in gen_mxu_s16mad()
1311 pad = extract32(ctx->opcode, 25, 1); in gen_mxu_s16mad()
1355 * Q8MUL XRa, XRb, XRc, XRd - Parallel quad unsigned 8 bit multiply
1356 * Q8MULSU XRa, XRb, XRc, XRd - Parallel quad signed 8 bit multiply
1357 * Q8MAC XRa, XRb, XRc, XRd - Parallel quad unsigned 8 bit multiply
1359 * Q8MACSU XRa, XRb, XRc, XRd - Parallel quad signed 8 bit multiply
1376 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q8mul_mac()
1377 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q8mul_mac()
1378 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q8mul_mac()
1379 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_q8mul_mac()
1380 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_q8mul_mac()
1458 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q8madl()
1459 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q8madl()
1460 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q8madl()
1461 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_q8madl()
1462 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_q8madl()
1511 * S32LDD XRa, Rb, S12 - Load a word from memory to XRF
1512 * S32LDDR XRa, Rb, S12 - Load a word from memory to XRF
1514 * S32LDI XRa, Rb, S12 - Load a word from memory to XRF,
1516 * S32LDIR XRa, Rb, S12 - Load a word from memory to XRF,
1527 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32ldxx()
1528 s12 = sextract32(ctx->opcode, 10, 10); in gen_mxu_s32ldxx()
1529 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s32ldxx()
1535 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, in gen_mxu_s32ldxx()
1537 ctx->default_tcg_memop_mask); in gen_mxu_s32ldxx()
1546 * S32STD XRa, Rb, S12 - Store a word from XRF to memory
1547 * S32STDR XRa, Rb, S12 - Store a word from XRF to memory
1549 * S32SDI XRa, Rb, S12 - Store a word from XRF to memory,
1551 * S32SDIR XRa, Rb, S12 - Store a word from XRF to memory,
1562 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32stxx()
1563 s12 = sextract32(ctx->opcode, 10, 10); in gen_mxu_s32stxx()
1564 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s32stxx()
1571 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, in gen_mxu_s32stxx()
1573 ctx->default_tcg_memop_mask); in gen_mxu_s32stxx()
1581 * S32LDDV XRa, Rb, Rc, STRD2 - Load a word from memory to XRF
1582 * S32LDDVR XRa, Rb, Rc, STRD2 - Load a word from memory to XRF
1584 * S32LDIV XRa, Rb, Rc, STRD2 - Load a word from memory to XRF,
1586 * S32LDIVR XRa, Rb, Rc, STRD2 - Load a word from memory to XRF,
1598 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32ldxvx()
1599 Rc = extract32(ctx->opcode, 16, 5); in gen_mxu_s32ldxvx()
1600 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s32ldxvx()
1607 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, in gen_mxu_s32ldxvx()
1609 ctx->default_tcg_memop_mask); in gen_mxu_s32ldxvx()
1618 * LXW Ra, Rb, Rc, STRD2 - Load a word from memory to GPR
1619 * LXB Ra, Rb, Rc, STRD2 - Load a byte from memory to GPR,
1621 * LXH Ra, Rb, Rc, STRD2 - Load a byte from memory to GPR,
1623 * LXBU Ra, Rb, Rc, STRD2 - Load a halfword from memory to GPR,
1625 * LXHU Ra, Rb, Rc, STRD2 - Load a halfword from memory to GPR,
1636 Ra = extract32(ctx->opcode, 11, 5); in gen_mxu_lxx()
1637 Rc = extract32(ctx->opcode, 16, 5); in gen_mxu_lxx()
1638 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_lxx()
1645 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mop | ctx->default_tcg_memop_mask); in gen_mxu_lxx()
1650 * S32STDV XRa, Rb, Rc, STRD2 - Load a word from memory to XRF
1651 * S32STDVR XRa, Rb, Rc, STRD2 - Load a word from memory to XRF
1653 * S32SDIV XRa, Rb, Rc, STRD2 - Load a word from memory to XRF,
1655 * S32SDIVR XRa, Rb, Rc, STRD2 - Load a word from memory to XRF,
1667 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32stxvx()
1668 Rc = extract32(ctx->opcode, 16, 5); in gen_mxu_s32stxvx()
1669 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s32stxvx()
1677 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, in gen_mxu_s32stxvx()
1679 ctx->default_tcg_memop_mask); in gen_mxu_s32stxvx()
1702 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_S32NOR()
1703 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_S32NOR()
1704 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_S32NOR()
1705 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_S32NOR()
1708 /* opcode padding incorrect -> do nothing */ in gen_mxu_S32NOR()
1710 /* destination is zero register -> do nothing */ in gen_mxu_S32NOR()
1712 /* both operands zero registers -> just set destination to all 1s */ in gen_mxu_S32NOR()
1713 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0xFFFFFFFF); in gen_mxu_S32NOR()
1715 /* XRb zero register -> just set destination to the negation of XRc */ in gen_mxu_S32NOR()
1716 tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); in gen_mxu_S32NOR()
1718 /* XRa zero register -> just set destination to the negation of XRb */ in gen_mxu_S32NOR()
1719 tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32NOR()
1721 /* both operands same -> just set destination to the negation of XRb */ in gen_mxu_S32NOR()
1722 tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32NOR()
1725 tcg_gen_nor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]); in gen_mxu_S32NOR()
1738 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_S32AND()
1739 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_S32AND()
1740 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_S32AND()
1741 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_S32AND()
1744 /* opcode padding incorrect -> do nothing */ in gen_mxu_S32AND()
1746 /* destination is zero register -> do nothing */ in gen_mxu_S32AND()
1748 /* one of operands zero register -> just set destination to all 0s */ in gen_mxu_S32AND()
1749 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_S32AND()
1751 /* both operands same -> just set destination to one of them */ in gen_mxu_S32AND()
1752 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32AND()
1755 tcg_gen_and_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]); in gen_mxu_S32AND()
1768 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_S32OR()
1769 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_S32OR()
1770 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_S32OR()
1771 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_S32OR()
1774 /* opcode padding incorrect -> do nothing */ in gen_mxu_S32OR()
1776 /* destination is zero register -> do nothing */ in gen_mxu_S32OR()
1778 /* both operands zero registers -> just set destination to all 0s */ in gen_mxu_S32OR()
1779 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_S32OR()
1781 /* XRb zero register -> just set destination to the content of XRc */ in gen_mxu_S32OR()
1782 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); in gen_mxu_S32OR()
1784 /* XRc zero register -> just set destination to the content of XRb */ in gen_mxu_S32OR()
1785 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32OR()
1787 /* both operands same -> just set destination to one of them */ in gen_mxu_S32OR()
1788 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32OR()
1791 tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]); in gen_mxu_S32OR()
1804 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_S32XOR()
1805 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_S32XOR()
1806 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_S32XOR()
1807 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_S32XOR()
1810 /* opcode padding incorrect -> do nothing */ in gen_mxu_S32XOR()
1812 /* destination is zero register -> do nothing */ in gen_mxu_S32XOR()
1814 /* both operands zero registers -> just set destination to all 0s */ in gen_mxu_S32XOR()
1815 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_S32XOR()
1817 /* XRb zero register -> just set destination to the content of XRc */ in gen_mxu_S32XOR()
1818 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); in gen_mxu_S32XOR()
1820 /* XRc zero register -> just set destination to the content of XRb */ in gen_mxu_S32XOR()
1821 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32XOR()
1823 /* both operands same -> just set destination to all 0s */ in gen_mxu_S32XOR()
1824 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_S32XOR()
1827 tcg_gen_xor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]); in gen_mxu_S32XOR()
1843 * Dual 32-bit shift left from XRb and XRc to SFT4
1846 * Dual 32-bit shift logic right from XRb and XRc
1849 * Dual 32-bit shift arithmetic right from XRb and XRc
1856 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d32sxx()
1857 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d32sxx()
1858 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d32sxx()
1859 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_d32sxx()
1860 sft4 = extract32(ctx->opcode, 22, 4); in gen_mxu_d32sxx()
1886 * Dual 32-bit shift left from XRa and XRd to rs[3:0]
1889 * Dual 32-bit shift logic right from XRa and XRd to rs[3:0]
1892 * Dual 32-bit shift arithmetic right from XRa and XRd to rs[3:0]
1899 XRa = extract32(ctx->opcode, 10, 4); in gen_mxu_d32sxxv()
1900 XRd = extract32(ctx->opcode, 14, 4); in gen_mxu_d32sxxv()
1901 rs = extract32(ctx->opcode, 21, 5); in gen_mxu_d32sxxv()
1930 * Dual shift arithmetic right 32-bit integers in XRb and XRc
1934 * Dual shift arithmetic right 32-bit integers in XRb and XRc
1941 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d32sarl()
1942 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d32sarl()
1943 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d32sarl()
1944 rb = extract32(ctx->opcode, 21, 5); in gen_mxu_d32sarl()
1947 /* destination is zero register -> do nothing */ in gen_mxu_d32sarl()
1972 * Quad 16-bit shift left from XRb and XRc to SFT4
1975 * Quad 16-bit shift logic right from XRb and XRc
1978 * Quad 16-bit shift arithmetic right from XRb and XRc
1985 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q16sxx()
1986 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q16sxx()
1987 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q16sxx()
1988 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_q16sxx()
1989 sft4 = extract32(ctx->opcode, 22, 4); in gen_mxu_q16sxx()
2038 * Quad 16-bit shift left from XRa and XRd to rs[3:0]
2041 * Quad 16-bit shift logic right from XRa and XRd to rs[3:0]
2044 * Quad 16-bit shift arithmetic right from XRa and XRd to rs[3:0]
2051 XRa = extract32(ctx->opcode, 10, 4); in gen_mxu_q16sxxv()
2052 XRd = extract32(ctx->opcode, 14, 4); in gen_mxu_q16sxxv()
2053 rs = extract32(ctx->opcode, 21, 5); in gen_mxu_q16sxxv()
2120 * Update XRa with the maximum of signed 32-bit integers contained
2124 * Update XRa with the minimum of signed 32-bit integers contained
2131 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_S32MAX_S32MIN()
2132 opc = extract32(ctx->opcode, 18, 3); in gen_mxu_S32MAX_S32MIN()
2133 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_S32MAX_S32MIN()
2134 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_S32MAX_S32MIN()
2135 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_S32MAX_S32MIN()
2138 /* opcode padding incorrect -> do nothing */ in gen_mxu_S32MAX_S32MIN()
2140 /* destination is zero register -> do nothing */ in gen_mxu_S32MAX_S32MIN()
2142 /* both operands zero registers -> just set destination to zero */ in gen_mxu_S32MAX_S32MIN()
2143 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_S32MAX_S32MIN()
2145 /* exactly one operand is zero register - find which one is not...*/ in gen_mxu_S32MAX_S32MIN()
2149 tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); in gen_mxu_S32MAX_S32MIN()
2151 tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); in gen_mxu_S32MAX_S32MIN()
2154 /* both operands same -> just set destination to one of them */ in gen_mxu_S32MAX_S32MIN()
2155 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32MAX_S32MIN()
2159 tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], in gen_mxu_S32MAX_S32MIN()
2160 mxu_gpr[XRc - 1]); in gen_mxu_S32MAX_S32MIN()
2162 tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], in gen_mxu_S32MAX_S32MIN()
2163 mxu_gpr[XRc - 1]); in gen_mxu_S32MAX_S32MIN()
2170 * Update XRa with the 16-bit-wise maximums of signed integers
2174 * Update XRa with the 16-bit-wise minimums of signed integers
2181 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_D16MAX_D16MIN()
2182 opc = extract32(ctx->opcode, 18, 3); in gen_mxu_D16MAX_D16MIN()
2183 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_D16MAX_D16MIN()
2184 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_D16MAX_D16MIN()
2185 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_D16MAX_D16MIN()
2188 /* opcode padding incorrect -> do nothing */ in gen_mxu_D16MAX_D16MIN()
2190 /* destination is zero register -> do nothing */ in gen_mxu_D16MAX_D16MIN()
2192 /* both operands zero registers -> just set destination to zero */ in gen_mxu_D16MAX_D16MIN()
2193 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_D16MAX_D16MIN()
2195 /* exactly one operand is zero register - find which one is not...*/ in gen_mxu_D16MAX_D16MIN()
2197 /* ...and do half-word-wise max/min with one operand 0 */ in gen_mxu_D16MAX_D16MIN()
2202 /* the left half-word first */ in gen_mxu_D16MAX_D16MIN()
2203 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000); in gen_mxu_D16MAX_D16MIN()
2210 /* the right half-word */ in gen_mxu_D16MAX_D16MIN()
2211 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FFFF); in gen_mxu_D16MAX_D16MIN()
2212 /* move half-words to the leftmost position */ in gen_mxu_D16MAX_D16MIN()
2220 /* return resulting half-words to its original position */ in gen_mxu_D16MAX_D16MIN()
2223 tcg_gen_or_i32(mxu_gpr[XRa - 1], t2, t0); in gen_mxu_D16MAX_D16MIN()
2225 /* both operands same -> just set destination to one of them */ in gen_mxu_D16MAX_D16MIN()
2226 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_D16MAX_D16MIN()
2233 /* the left half-word first */ in gen_mxu_D16MAX_D16MIN()
2234 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000); in gen_mxu_D16MAX_D16MIN()
2235 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); in gen_mxu_D16MAX_D16MIN()
2242 /* the right half-word */ in gen_mxu_D16MAX_D16MIN()
2243 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); in gen_mxu_D16MAX_D16MIN()
2244 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FFFF); in gen_mxu_D16MAX_D16MIN()
2245 /* move half-words to the leftmost position */ in gen_mxu_D16MAX_D16MIN()
2254 /* return resulting half-words to its original position */ in gen_mxu_D16MAX_D16MIN()
2257 tcg_gen_or_i32(mxu_gpr[XRa - 1], t2, t0); in gen_mxu_D16MAX_D16MIN()
2263 * Update XRa with the 8-bit-wise maximums of signed integers
2267 * Update XRa with the 8-bit-wise minimums of signed integers
2274 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_Q8MAX_Q8MIN()
2275 opc = extract32(ctx->opcode, 18, 3); in gen_mxu_Q8MAX_Q8MIN()
2276 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_Q8MAX_Q8MIN()
2277 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_Q8MAX_Q8MIN()
2278 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_Q8MAX_Q8MIN()
2281 /* opcode padding incorrect -> do nothing */ in gen_mxu_Q8MAX_Q8MIN()
2283 /* destination is zero register -> do nothing */ in gen_mxu_Q8MAX_Q8MIN()
2285 /* both operands zero registers -> just set destination to zero */ in gen_mxu_Q8MAX_Q8MIN()
2286 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_Q8MAX_Q8MIN()
2288 /* exactly one operand is zero register - make it be the first...*/ in gen_mxu_Q8MAX_Q8MIN()
2290 /* ...and do byte-wise max/min with one operand 0 */ in gen_mxu_Q8MAX_Q8MIN()
2297 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000); in gen_mxu_Q8MAX_Q8MIN()
2305 for (i = 2; i >= 0; i--) { in gen_mxu_Q8MAX_Q8MIN()
2307 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF << (8 * i)); in gen_mxu_Q8MAX_Q8MIN()
2309 tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); in gen_mxu_Q8MAX_Q8MIN()
2317 tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); in gen_mxu_Q8MAX_Q8MIN()
2323 /* both operands same -> just set destination to one of them */ in gen_mxu_Q8MAX_Q8MIN()
2324 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_Q8MAX_Q8MIN()
2333 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000); in gen_mxu_Q8MAX_Q8MIN()
2334 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); in gen_mxu_Q8MAX_Q8MIN()
2342 for (i = 2; i >= 0; i--) { in gen_mxu_Q8MAX_Q8MIN()
2344 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF << (8 * i)); in gen_mxu_Q8MAX_Q8MIN()
2345 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF << (8 * i)); in gen_mxu_Q8MAX_Q8MIN()
2347 tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); in gen_mxu_Q8MAX_Q8MIN()
2348 tcg_gen_shli_i32(t1, t1, 8 * (3 - i)); in gen_mxu_Q8MAX_Q8MIN()
2356 tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); in gen_mxu_Q8MAX_Q8MIN()
2367 * on per-byte basis.
2372 * on per-byte basis.
2379 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_q8slt()
2380 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q8slt()
2381 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q8slt()
2382 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q8slt()
2385 /* opcode padding incorrect -> do nothing */ in gen_mxu_q8slt()
2387 /* destination is zero register -> do nothing */ in gen_mxu_q8slt()
2389 /* both operands zero registers -> just set destination to zero */ in gen_mxu_q8slt()
2390 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_q8slt()
2392 /* both operands same registers -> just set destination to zero */ in gen_mxu_q8slt()
2393 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_q8slt()
2430 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_S32SLT()
2431 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_S32SLT()
2432 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_S32SLT()
2433 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_S32SLT()
2436 /* opcode padding incorrect -> do nothing */ in gen_mxu_S32SLT()
2438 /* destination is zero register -> do nothing */ in gen_mxu_S32SLT()
2440 /* both operands zero registers -> just set destination to zero */ in gen_mxu_S32SLT()
2441 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_S32SLT()
2443 /* both operands same registers -> just set destination to zero */ in gen_mxu_S32SLT()
2444 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_S32SLT()
2452 tcg_gen_setcond_tl(TCG_COND_LT, mxu_gpr[XRa - 1], t0, t1); in gen_mxu_S32SLT()
2459 * on per-word basis.
2466 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_D16SLT()
2467 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_D16SLT()
2468 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_D16SLT()
2469 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_D16SLT()
2472 /* opcode padding incorrect -> do nothing */ in gen_mxu_D16SLT()
2474 /* destination is zero register -> do nothing */ in gen_mxu_D16SLT()
2476 /* both operands zero registers -> just set destination to zero */ in gen_mxu_D16SLT()
2477 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_D16SLT()
2479 /* both operands same registers -> just set destination to zero */ in gen_mxu_D16SLT()
2480 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_D16SLT()
2498 tcg_gen_or_tl(mxu_gpr[XRa - 1], t2, t0); in gen_mxu_D16SLT()
2505 * on per-word basis, rounding down.
2510 * on per-word basis, math rounding 4/5.
2517 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_d16avg()
2518 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d16avg()
2519 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d16avg()
2520 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16avg()
2523 /* opcode padding incorrect -> do nothing */ in gen_mxu_d16avg()
2525 /* destination is zero register -> do nothing */ in gen_mxu_d16avg()
2527 /* both operands zero registers -> just set destination to zero */ in gen_mxu_d16avg()
2528 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_d16avg()
2530 /* both operands same registers -> just set destination to same */ in gen_mxu_d16avg()
2531 tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_d16avg()
2565 * on per-byte basis, rounding down.
2570 * on per-word basis, math rounding 4/5.
2577 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_q8avg()
2578 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q8avg()
2579 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q8avg()
2580 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q8avg()
2583 /* opcode padding incorrect -> do nothing */ in gen_mxu_q8avg()
2585 /* destination is zero register -> do nothing */ in gen_mxu_q8avg()
2587 /* both operands zero registers -> just set destination to zero */ in gen_mxu_q8avg()
2588 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_q8avg()
2590 /* both operands same registers -> just set destination to same */ in gen_mxu_q8avg()
2591 tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_q8avg()
2620 * Quadruple 8-bit packed conditional move where
2626 * Quadruple 8-bit packed conditional move where
2635 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q8movzn()
2636 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q8movzn()
2637 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q8movzn()
2681 * Double 16-bit packed conditional move where
2687 * Double 16-bit packed conditional move where
2696 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16movzn()
2697 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d16movzn()
2698 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d16movzn()
2728 * Quadruple 32-bit conditional move where
2734 * Single 32-bit conditional move where
2743 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32movzn()
2744 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_s32movzn()
2745 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_s32movzn()
2769 * Update XRa if XRc < 0 by value of 0 - XRb
2776 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_S32CPS()
2777 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_S32CPS()
2778 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_S32CPS()
2779 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_S32CPS()
2782 /* opcode padding incorrect -> do nothing */ in gen_mxu_S32CPS()
2784 /* destination is zero register -> do nothing */ in gen_mxu_S32CPS()
2786 /* XRc make no sense 0 - 0 = 0 -> just set destination to zero */ in gen_mxu_S32CPS()
2787 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_S32CPS()
2789 /* condition always false -> just move XRb to XRa */ in gen_mxu_S32CPS()
2790 tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32CPS()
2797 tcg_gen_brcondi_tl(TCG_COND_GE, mxu_gpr[XRc - 1], 0, l_not_less); in gen_mxu_S32CPS()
2798 tcg_gen_neg_tl(t0, mxu_gpr[XRb - 1]); in gen_mxu_S32CPS()
2809 * Update XRa[0..1] if XRc[0..1] < 0 by value of 0 - XRb[0..1]
2816 pad = extract32(ctx->opcode, 21, 5); in gen_mxu_D16CPS()
2817 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_D16CPS()
2818 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_D16CPS()
2819 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_D16CPS()
2822 /* opcode padding incorrect -> do nothing */ in gen_mxu_D16CPS()
2824 /* destination is zero register -> do nothing */ in gen_mxu_D16CPS()
2826 /* XRc make no sense 0 - 0 = 0 -> just set destination to zero */ in gen_mxu_D16CPS()
2827 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_D16CPS()
2829 /* condition always false -> just move XRb to XRa */ in gen_mxu_D16CPS()
2830 tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_D16CPS()
2839 tcg_gen_sextract_tl(t0, mxu_gpr[XRc - 1], 16, 16); in gen_mxu_D16CPS()
2840 tcg_gen_sextract_tl(t1, mxu_gpr[XRb - 1], 16, 16); in gen_mxu_D16CPS()
2847 tcg_gen_sextract_tl(t0, mxu_gpr[XRc - 1], 0, 16); in gen_mxu_D16CPS()
2849 tcg_gen_sextract_tl(t0, mxu_gpr[XRb - 1], 0, 16); in gen_mxu_D16CPS()
2854 tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 0, 16); in gen_mxu_D16CPS()
2857 tcg_gen_deposit_tl(mxu_gpr[XRa - 1], t1, t0, 0, 16); in gen_mxu_D16CPS()
2863 * Gets absolute difference for quadruple of 8-bit
2866 * a.k.a. XRa[0..3] = abs(XRb[0..3] - XRc[0..3]);
2872 pad = extract32(ctx->opcode, 21, 3); in gen_mxu_Q8ABD()
2873 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_Q8ABD()
2874 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_Q8ABD()
2875 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_Q8ABD()
2878 /* opcode padding incorrect -> do nothing */ in gen_mxu_Q8ABD()
2880 /* destination is zero register -> do nothing */ in gen_mxu_Q8ABD()
2882 /* both operands zero registers -> just set destination to zero */ in gen_mxu_Q8ABD()
2883 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_Q8ABD()
2911 * Add/subtract quadruple of 8-bit packed in XRb
2918 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_Q8ADD()
2919 pad = extract32(ctx->opcode, 21, 3); in gen_mxu_Q8ADD()
2920 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_Q8ADD()
2921 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_Q8ADD()
2922 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_Q8ADD()
2925 /* opcode padding incorrect -> do nothing */ in gen_mxu_Q8ADD()
2927 /* destination is zero register -> do nothing */ in gen_mxu_Q8ADD()
2929 /* both operands zero registers -> just set destination to zero */ in gen_mxu_Q8ADD()
2930 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_Q8ADD()
2976 * Add/subtract quadruple of 8-bit packed in XRb
2978 * to 16-bit and put results as packed 16-bit data
2983 * Add/subtract quadruple of 8-bit packed in XRb
2985 * to 16-bit and accumulate results as packed 16-bit data
2993 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_q8adde()
2994 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_q8adde()
2995 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q8adde()
2996 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q8adde()
2997 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q8adde()
3000 /* both operands zero registers -> just set destination to zero */ in gen_mxu_q8adde()
3002 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_q8adde()
3005 tcg_gen_movi_tl(mxu_gpr[XRd - 1], 0); in gen_mxu_q8adde()
3070 * Double parallel add of quadruple unsigned 8-bit together
3071 * with zero extending to 16-bit data.
3073 * Double parallel add of quadruple unsigned 8-bit together
3074 * with zero extending to 16-bit data and adding 2 to each
3081 pad = extract32(ctx->opcode, 24, 2); in gen_mxu_d8sum()
3082 pad2 = extract32(ctx->opcode, 18, 4); in gen_mxu_d8sum()
3083 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d8sum()
3084 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d8sum()
3085 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d8sum()
3088 /* opcode padding incorrect -> do nothing */ in gen_mxu_d8sum()
3090 /* destination is zero register -> do nothing */ in gen_mxu_d8sum()
3092 /* both operands zero registers -> just set destination to zero */ in gen_mxu_d8sum()
3093 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_d8sum()
3104 tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 0, 8); in gen_mxu_d8sum()
3105 tcg_gen_extract_tl(t1, mxu_gpr[XRb - 1], 8, 8); in gen_mxu_d8sum()
3106 tcg_gen_extract_tl(t2, mxu_gpr[XRb - 1], 16, 8); in gen_mxu_d8sum()
3107 tcg_gen_extract_tl(t3, mxu_gpr[XRb - 1], 24, 8); in gen_mxu_d8sum()
3115 tcg_gen_extract_tl(t0, mxu_gpr[XRc - 1], 0, 8); in gen_mxu_d8sum()
3116 tcg_gen_extract_tl(t1, mxu_gpr[XRc - 1], 8, 8); in gen_mxu_d8sum()
3117 tcg_gen_extract_tl(t2, mxu_gpr[XRc - 1], 16, 8); in gen_mxu_d8sum()
3118 tcg_gen_extract_tl(t3, mxu_gpr[XRc - 1], 24, 8); in gen_mxu_d8sum()
3132 tcg_gen_or_tl(mxu_gpr[XRa - 1], t4, t5); in gen_mxu_d8sum()
3137 * Q16ADD XRa, XRb, XRc, XRd, aptn2, optn2 - Quad packed
3138 * 16-bit pattern addition.
3144 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_q16add()
3145 optn2 = extract32(ctx->opcode, 22, 2); in gen_mxu_q16add()
3146 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_q16add()
3147 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q16add()
3148 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q16add()
3149 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q16add()
3217 tcg_gen_or_tl(mxu_gpr[XRa - 1], t4, t5); in gen_mxu_q16add()
3218 tcg_gen_or_tl(mxu_gpr[XRd - 1], t0, t1); in gen_mxu_q16add()
3222 * Q16ACC XRa, XRb, XRc, XRd, aptn2 - Quad packed
3223 * 16-bit addition/subtraction with accumulate.
3229 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_q16acc()
3230 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_q16acc()
3231 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q16acc()
3232 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q16acc()
3233 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q16acc()
3259 case MXU_APTN2_AS: /* lop +, rop - */ in gen_mxu_q16acc()
3265 case MXU_APTN2_SA: /* lop -, rop + */ in gen_mxu_q16acc()
3271 case MXU_APTN2_SS: /* lop -, rop - */ in gen_mxu_q16acc()
3280 tcg_gen_add_tl(t0, mxu_gpr[XRa - 1], s0); in gen_mxu_q16acc()
3282 tcg_gen_extract_tl(t1, mxu_gpr[XRa - 1], 16, 16); in gen_mxu_q16acc()
3285 tcg_gen_or_tl(mxu_gpr[XRa - 1], t1, t0); in gen_mxu_q16acc()
3289 tcg_gen_add_tl(t0, mxu_gpr[XRd - 1], s2); in gen_mxu_q16acc()
3291 tcg_gen_extract_tl(t1, mxu_gpr[XRd - 1], 16, 16); in gen_mxu_q16acc()
3294 tcg_gen_or_tl(mxu_gpr[XRd - 1], t1, t0); in gen_mxu_q16acc()
3299 * Q16ACCM XRa, XRb, XRc, XRd, aptn2 - Quad packed
3300 * 16-bit accumulate.
3306 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_q16accm()
3307 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_q16accm()
3308 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q16accm()
3309 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q16accm()
3310 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q16accm()
3340 tcg_gen_or_tl(mxu_gpr[XRa - 1], a1, a0); in gen_mxu_q16accm()
3363 tcg_gen_or_tl(mxu_gpr[XRd - 1], a1, a0); in gen_mxu_q16accm()
3369 * D16ASUM XRa, XRb, XRc, XRd, aptn2 - Double packed
3370 * 16-bit sign extended addition and accumulate.
3376 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_d16asum()
3377 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_d16asum()
3378 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d16asum()
3379 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d16asum()
3380 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16asum()
3395 tcg_gen_sub_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); in gen_mxu_d16asum()
3397 tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); in gen_mxu_d16asum()
3406 tcg_gen_sub_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t0); in gen_mxu_d16asum()
3408 tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t0); in gen_mxu_d16asum()
3414 * D32ADD XRa, XRb, XRc, XRd, aptn2 - Double
3417 * D32ADDC XRa, XRb, XRc, XRd, aptn2 - Double
3424 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_d32add()
3425 addc = extract32(ctx->opcode, 22, 2); in gen_mxu_d32add()
3426 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_d32add()
3427 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d32add()
3428 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d32add()
3429 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d32add()
3437 /* opcode incorrect -> do nothing */ in gen_mxu_d32add()
3440 /* destinations are zero register -> do nothing */ in gen_mxu_d32add()
3450 tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); in gen_mxu_d32add()
3455 tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1); in gen_mxu_d32add()
3459 /* destinations are zero register -> do nothing */ in gen_mxu_d32add()
3499 * D32ACC XRa, XRb, XRc, XRd, aptn2 - Double
3506 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_d32acc()
3507 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_d32acc()
3508 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d32acc()
3509 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d32acc()
3510 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d32acc()
3517 /* destinations are zero register -> do nothing */ in gen_mxu_d32acc()
3528 tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2); in gen_mxu_d32acc()
3536 tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2); in gen_mxu_d32acc()
3542 * D32ACCM XRa, XRb, XRc, XRd, aptn2 - Double
3549 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_d32accm()
3550 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_d32accm()
3551 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d32accm()
3552 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d32accm()
3553 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d32accm()
3560 /* destinations are zero register -> do nothing */ in gen_mxu_d32accm()
3568 tcg_gen_sub_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2); in gen_mxu_d32accm()
3570 tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2); in gen_mxu_d32accm()
3576 tcg_gen_sub_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2); in gen_mxu_d32accm()
3578 tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2); in gen_mxu_d32accm()
3585 * D32ASUM XRa, XRb, XRc, XRd, aptn2 - Double
3592 aptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_d32asum()
3593 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_d32asum()
3594 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_d32asum()
3595 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_d32asum()
3596 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d32asum()
3602 /* destinations are zero register -> do nothing */ in gen_mxu_d32asum()
3609 tcg_gen_sub_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); in gen_mxu_d32asum()
3611 tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); in gen_mxu_d32asum()
3616 tcg_gen_sub_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1); in gen_mxu_d32asum()
3618 tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1); in gen_mxu_d32asum()
3636 * Extract bits5 bits from 64-bit pair {XRa:XRd}
3649 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32extr()
3650 XRd = extract32(ctx->opcode, 10, 4); in gen_mxu_s32extr()
3651 bits5 = extract32(ctx->opcode, 16, 5); in gen_mxu_s32extr()
3652 rs = extract32(ctx->opcode, 21, 5); in gen_mxu_s32extr()
3654 /* {tmp} = {XRa:XRd} >> (64 - rt - bits5); */ in gen_mxu_s32extr()
3686 * Extract rt[4:0] bits from 64-bit pair {XRa:XRd}
3704 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32extrv()
3705 XRd = extract32(ctx->opcode, 10, 4); in gen_mxu_s32extrv()
3706 rt = extract32(ctx->opcode, 16, 5); in gen_mxu_s32extrv()
3707 rs = extract32(ctx->opcode, 21, 5); in gen_mxu_s32extrv()
3709 /* {tmp} = {XRa:XRd} >> (64 - rs - rt) */ in gen_mxu_s32extrv()
3754 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32lui()
3755 s8 = extract32(ctx->opcode, 10, 8); in gen_mxu_s32lui()
3756 pad = extract32(ctx->opcode, 21, 2); in gen_mxu_s32lui()
3757 optn3 = extract32(ctx->opcode, 23, 3); in gen_mxu_s32lui()
3760 /* opcode padding incorrect -> do nothing */ in gen_mxu_s32lui()
3762 /* destination is zero register -> do nothing */ in gen_mxu_s32lui()
3800 * Packs four 16-bit signed integers in XRb and XRc to
3801 * four saturated unsigned 8-bit into XRa.
3808 pad = extract32(ctx->opcode, 21, 3); in gen_mxu_Q16SAT()
3809 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_Q16SAT()
3810 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_Q16SAT()
3811 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_Q16SAT()
3814 /* opcode padding incorrect -> do nothing */ in gen_mxu_Q16SAT()
3816 /* destination is zero register -> do nothing */ in gen_mxu_Q16SAT()
3832 tcg_gen_sari_tl(t0, mxu_gpr[XRb - 1], 16); in gen_mxu_Q16SAT()
3843 tcg_gen_shli_tl(t1, mxu_gpr[XRb - 1], 16); in gen_mxu_Q16SAT()
3868 tcg_gen_sari_tl(t0, mxu_gpr[XRc - 1], 16); in gen_mxu_Q16SAT()
3879 tcg_gen_shli_tl(t1, mxu_gpr[XRc - 1], 16); in gen_mxu_Q16SAT()
3901 * Determine sign of quad packed 16-bit signed values
3908 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_q16scop()
3909 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q16scop()
3910 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q16scop()
3911 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q16scop()
3988 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_s32sfl()
3989 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_s32sfl()
3990 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_s32sfl()
3991 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32sfl()
3992 ptn2 = extract32(ctx->opcode, 24, 2); in gen_mxu_s32sfl()
4065 XRd = extract32(ctx->opcode, 18, 4); in gen_mxu_q8sad()
4066 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_q8sad()
4067 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_q8sad()
4068 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q8sad()
4114 optn3 = extract32(ctx->opcode, 23, 3); in gen_mxu_S32ALNI()
4115 pad = extract32(ctx->opcode, 21, 2); in gen_mxu_S32ALNI()
4116 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_S32ALNI()
4117 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_S32ALNI()
4118 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_S32ALNI()
4121 /* opcode padding incorrect -> do nothing */ in gen_mxu_S32ALNI()
4123 /* destination is zero register -> do nothing */ in gen_mxu_S32ALNI()
4125 /* both operands zero registers -> just set destination to all 0s */ in gen_mxu_S32ALNI()
4126 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_S32ALNI()
4128 /* XRb zero register -> just appropriatelly shift XRc into XRa */ in gen_mxu_S32ALNI()
4131 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_S32ALNI()
4136 tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1], in gen_mxu_S32ALNI()
4137 8 * (4 - optn3)); in gen_mxu_S32ALNI()
4140 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); in gen_mxu_S32ALNI()
4144 /* XRc zero register -> just appropriatelly shift XRb into XRa */ in gen_mxu_S32ALNI()
4147 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32ALNI()
4152 tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3); in gen_mxu_S32ALNI()
4155 tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); in gen_mxu_S32ALNI()
4159 /* both operands same -> just rotation or moving from any of them */ in gen_mxu_S32ALNI()
4163 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32ALNI()
4168 tcg_gen_rotli_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3); in gen_mxu_S32ALNI()
4178 /* +---------------+ */ in gen_mxu_S32ALNI()
4180 /* +-------+-------+ */ in gen_mxu_S32ALNI()
4185 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); in gen_mxu_S32ALNI()
4192 /* +-------------------+ */ in gen_mxu_S32ALNI()
4194 /* +---------+---------+ */ in gen_mxu_S32ALNI()
4202 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FFFFFF); in gen_mxu_S32ALNI()
4205 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); in gen_mxu_S32ALNI()
4208 tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); in gen_mxu_S32ALNI()
4215 /* +-------------------+ */ in gen_mxu_S32ALNI()
4217 /* +---------+---------+ */ in gen_mxu_S32ALNI()
4225 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); in gen_mxu_S32ALNI()
4228 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); in gen_mxu_S32ALNI()
4231 tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); in gen_mxu_S32ALNI()
4238 /* +-------------------+ */ in gen_mxu_S32ALNI()
4240 /* +---------+---------+ */ in gen_mxu_S32ALNI()
4248 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x000000FF); in gen_mxu_S32ALNI()
4251 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFFFF00); in gen_mxu_S32ALNI()
4254 tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); in gen_mxu_S32ALNI()
4261 /* +---------------+ */ in gen_mxu_S32ALNI()
4263 /* +-------+-------+ */ in gen_mxu_S32ALNI()
4268 tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); in gen_mxu_S32ALNI()
4284 rs = extract32(ctx->opcode, 21, 5); in gen_mxu_S32ALN()
4285 XRc = extract32(ctx->opcode, 14, 4); in gen_mxu_S32ALN()
4286 XRb = extract32(ctx->opcode, 10, 4); in gen_mxu_S32ALN()
4287 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_S32ALN()
4290 /* destination is zero register -> do nothing */ in gen_mxu_S32ALN()
4292 /* both operands zero registers -> just set destination to all 0s */ in gen_mxu_S32ALN()
4293 tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0); in gen_mxu_S32ALN()
4320 tcg_gen_or_tl(mxu_gpr[XRa - 1], t0, t1); in gen_mxu_S32ALN()
4352 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s32madd_sub()
4353 XRd = extract32(ctx->opcode, 10, 4); in gen_mxu_s32madd_sub()
4354 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32madd_sub()
4355 Rc = extract32(ctx->opcode, 21, 5); in gen_mxu_s32madd_sub()
4406 uint32_t opcode = extract32(ctx->opcode, 18, 3); in decode_opc_mxu__pool00()
4436 uint32_t opcode = extract32(ctx->opcode, 0, 6); in decode_opc_mxu_s32madd_sub()
4437 uint32_t pad = extract32(ctx->opcode, 14, 2); in decode_opc_mxu_s32madd_sub()
4465 uint32_t opcode = extract32(ctx->opcode, 18, 3); in decode_opc_mxu__pool01()
4498 uint32_t opcode = extract32(ctx->opcode, 18, 3); in decode_opc_mxu__pool02()
4522 uint32_t opcode = extract32(ctx->opcode, 24, 2); in decode_opc_mxu__pool03()
4540 uint32_t reversed = extract32(ctx->opcode, 20, 1); in decode_opc_mxu__pool04()
4541 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool04()
4553 uint32_t reversed = extract32(ctx->opcode, 20, 1); in decode_opc_mxu__pool05()
4554 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool05()
4566 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool06()
4567 uint32_t strd2 = extract32(ctx->opcode, 14, 2); in decode_opc_mxu__pool06()
4586 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool07()
4587 uint32_t strd2 = extract32(ctx->opcode, 14, 2); in decode_opc_mxu__pool07()
4606 uint32_t reversed = extract32(ctx->opcode, 20, 1); in decode_opc_mxu__pool08()
4607 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool08()
4619 uint32_t reversed = extract32(ctx->opcode, 20, 1); in decode_opc_mxu__pool09()
4620 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool09()
4632 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool10()
4633 uint32_t strd2 = extract32(ctx->opcode, 14, 2); in decode_opc_mxu__pool10()
4652 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool11()
4653 uint32_t strd2 = extract32(ctx->opcode, 14, 2); in decode_opc_mxu__pool11()
4672 uint32_t opcode = extract32(ctx->opcode, 22, 2); in decode_opc_mxu__pool12()
4693 uint32_t opcode = extract32(ctx->opcode, 22, 2); in decode_opc_mxu__pool13()
4714 uint32_t opcode = extract32(ctx->opcode, 22, 2); in decode_opc_mxu__pool14()
4735 uint32_t opcode = extract32(ctx->opcode, 14, 2); in decode_opc_mxu__pool15()
4759 uint32_t opcode = extract32(ctx->opcode, 18, 3); in decode_opc_mxu__pool16()
4795 uint32_t opcode = extract32(ctx->opcode, 6, 3); in decode_opc_mxu__pool17()
4796 uint32_t strd2 = extract32(ctx->opcode, 9, 2); in decode_opc_mxu__pool17()
4829 uint32_t opcode = extract32(ctx->opcode, 18, 3); in decode_opc_mxu__pool18()
4859 uint32_t opcode = extract32(ctx->opcode, 22, 4); in decode_opc_mxu__pool19()
4877 uint32_t opcode = extract32(ctx->opcode, 18, 3); in decode_opc_mxu__pool20()
4907 uint32_t opcode = extract32(ctx->opcode, 22, 2); in decode_opc_mxu__pool21()