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123

/qemu/disas/
H A Dm68k.c35 fields is contiguous. We number the bits with 0 being the most significant
67 /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
74 very large number (e.g., given the exp_bias of 0x3fff and a 64
143 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
165 #define _m68k_undef 0
166 #define m68000 0x001
168 #define m68010 0x002
169 #define m68020 0x004
170 #define m68030 0x008
173 #define m68040 0x010
[all …]
/qemu/docs/specs/
H A Dppc-spapr-hcalls.rst17 All those hypercalls start at hcall number 0xf000 which correspond
20 ``H_RTAS (0xf000)``
35 ``r3``: ``H_RTAS (0xf000)``
46 ``H_LOGICAL_MEMOP (0xf001)``
70 ``r3 ``: ``H_LOGICAL_MEMOP (0xf001)``
79 ``0`` = 1 byte
91 ``0``: copy
/qemu/tests/tcg/aarch64/system/
H A Dsemiconsole.c12 #define SYS_READC 0x7
18 asm("hlt 0xf000" in __semi_call()
33 c = __semi_call(SYS_READC, 0); in main()
37 return 0; in main()
H A Dsemiheap.c13 #define SYS_HEAPINFO 0x16
19 asm("hlt 0xf000" in __semi_call()
77 for (i = 0; i < 512; i++) { in main()
81 for (i = 0; i < 512; i++) { in main()
92 return 0; in main()
H A Dboot.S16 #define semihosting_call hlt 0xf000
17 #define SYS_WRITEC 0x03 /* character to debug channel */
18 #define SYS_WRITE0 0x04 /* string to debug channel */
19 #define SYS_GET_CMDLINE 0x15 /* get command line */
20 #define SYS_EXIT 0x18
123 subs w11, w11, #'0'
169 orr x0, x0, #(1 << 0) /* NS = 1: Non-secure state */
178 cbz x0, el2_not_present /* If field is 0 no EL2 */
182 mov x0, #0x3c9 /* DAIF bits and EL2h mode (9) */
201 mov x0, #0x3c5 /* DAIF bits and EL1h mode (5) */
[all …]
/qemu/tests/tcg/aarch64/
H A Dsemicall.h14 asm("hlt 0xf000" in __semi_call()
/qemu/include/hw/s390x/
H A Dioinst.h31 #define SCSW_FLAGS_MASK_KEY 0xf000
32 #define SCSW_FLAGS_MASK_SCTL 0x0800
33 #define SCSW_FLAGS_MASK_ESWF 0x0400
34 #define SCSW_FLAGS_MASK_CC 0x0300
35 #define SCSW_FLAGS_MASK_FMT 0x0080
36 #define SCSW_FLAGS_MASK_PFCH 0x0040
37 #define SCSW_FLAGS_MASK_ISIC 0x0020
38 #define SCSW_FLAGS_MASK_ALCC 0x0010
39 #define SCSW_FLAGS_MASK_SSI 0x0008
40 #define SCSW_FLAGS_MASK_ZCC 0x0004
[all …]
/qemu/pc-bios/vof/
H A Dentry.S13 #define KVMPPC_HCALL_BASE 0xf000
14 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
15 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
17 . = 0x100 /* Do exactly as SLOF does */
/qemu/target/xtensa/core-lx106/
H A Dxtensa-modules.c.inc31 { "MMID", 89, 0 },
32 { "DDR", 104, 0 },
33 { "176", 176, 0 },
34 { "208", 208, 0 },
35 { "INTERRUPT", 226, 0 },
36 { "INTCLEAR", 227, 0 },
37 { "CCOUNT", 234, 0 },
38 { "PRID", 235, 0 },
39 { "ICOUNT", 236, 0 },
40 { "CCOMPARE0", 240, 0 },
[all …]
/qemu/include/hw/ppc/
H A Dmac_dbdma.h53 #define DBDMA_CONTROL 0x00
54 #define DBDMA_STATUS 0x01
55 #define DBDMA_CMDPTR_HI 0x02
56 #define DBDMA_CMDPTR_LO 0x03
57 #define DBDMA_INTR_SEL 0x04
58 #define DBDMA_BRANCH_SEL 0x05
59 #define DBDMA_WAIT_SEL 0x06
60 #define DBDMA_XFER_MODE 0x07
61 #define DBDMA_DATA2PTR_HI 0x08
62 #define DBDMA_DATA2PTR_LO 0x09
[all …]
H A Dspapr.h27 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
28 #define SPAPR_ENTRY_POINT 0x100
48 SPAPR_RESIZE_HPT_DEFAULT = 0,
59 #define SPAPR_CAP_HTM 0x00
61 #define SPAPR_CAP_VSX 0x01
63 #define SPAPR_CAP_DFP 0x02
65 #define SPAPR_CAP_CFPC 0x03
67 #define SPAPR_CAP_SBBC 0x04
69 #define SPAPR_CAP_IBS 0x05
71 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06
[all …]
H A Dspapr_nested.h7 #define GSB_HV_VCPU_IGNORED_ID 0x0000 /* An element whose value is ignored */
8 #define GSB_HV_VCPU_STATE_SIZE 0x0001 /* HV internal format VCPU state size */
9 #define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buffer */
10 #define GSB_VCPU_LPVR 0x0003 /* Logical PVR */
11 #define GSB_TB_OFFSET 0x0004 /* Timebase Offset */
12 #define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */
13 #define GSB_PROCESS_TBL 0x0006 /* Process Table */
14 /* RESERVED 0x0007 - 0x07FF */
15 #define GSB_L0_GUEST_HEAP_INUSE 0x0800 /* Guest Management Heap Size */
16 #define GSB_L0_GUEST_HEAP_MAX 0x0801 /* Guest Management Heap Max Size */
[all …]
/qemu/tests/qemu-iotests/
H A D07725 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
57 aio_write -P 10 0x200 0x200
62 off=0x1000
66 aio_write -P 10 $((off + 0x200)) 0x200
68 aio_write -P 11 $((off + 0x400)) 0x200
73 off=$((off + 0x1000))
79 aio_write -P 10 0x5000 0x200
81 aio_write -P 11 0x5200 0x200
82 aio_write -P 12 0x5400 0x200
[all …]
/qemu/hw/net/
H A Dpcnet.c27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
65 #define CSR_INIT(S) !!(((S)->csr[0])&0x0001)
66 #define CSR_STRT(S) !!(((S)->csr[0])&0x0002)
67 #define CSR_STOP(S) !!(((S)->csr[0])&0x0004)
68 #define CSR_TDMD(S) !!(((S)->csr[0])&0x0008)
69 #define CSR_TXON(S) !!(((S)->csr[0])&0x0010)
70 #define CSR_RXON(S) !!(((S)->csr[0])&0x0020)
71 #define CSR_INEA(S) !!(((S)->csr[0])&0x0040)
72 #define CSR_BSWP(S) !!(((S)->csr[3])&0x0004)
73 #define CSR_LAPPEN(S) !!(((S)->csr[3])&0x0020)
[all …]
H A Ddp8393x.c38 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
41 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
42 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
44 #define SONIC_CR 0x00
45 #define SONIC_DCR 0x01
46 #define SONIC_RCR 0x02
47 #define SONIC_TCR 0x03
48 #define SONIC_IMR 0x04
49 #define SONIC_ISR 0x05
50 #define SONIC_UTDA 0x06
[all …]
/qemu/hw/char/
H A Dstm32f2xx_usart.c43 return 0; in stm32f2xx_usart_can_receive()
53 qemu_set_irq(s->irq, 0); in stm32f2xx_update_irq()
81 s->usart_dr = 0x00000000; in stm32f2xx_usart_reset()
82 s->usart_brr = 0x00000000; in stm32f2xx_usart_reset()
83 s->usart_cr1 = 0x00000000; in stm32f2xx_usart_reset()
84 s->usart_cr2 = 0x00000000; in stm32f2xx_usart_reset()
85 s->usart_cr3 = 0x00000000; in stm32f2xx_usart_reset()
86 s->usart_gtpr = 0x00000000; in stm32f2xx_usart_reset()
96 uint64_t retvalue = 0; in stm32f2xx_usart_read()
104 retvalue = s->usart_dr & 0x3FF; in stm32f2xx_usart_read()
[all …]
/qemu/hw/pci-host/
H A Dsabre.c49 #define PBM_PCI_IMR_MASK 0x7fffffff
50 #define PBM_PCI_IMR_ENABLED 0x80000000
57 #define RESET_MASK 0xf8000000
58 #define RESET_WCMASK 0x98000000
59 #define RESET_WMASK 0x60000000
80 if (s->pci_irq_in == 0ULL) { in sabre_check_irqs()
83 for (i = 0; i < 32; i++) { in sabre_check_irqs()
104 qemu_set_irq(s->ivec_irqs[irq_num], 0); in sabre_clear_request()
127 case 0x30 ... 0x4f: /* DMA error registers */ in sabre_config_write()
130 case 0xc00 ... 0xc3f: /* PCI interrupt control */ in sabre_config_write()
[all …]
/qemu/tests/qtest/libqos/
H A Dahci.h33 #define PCI_DEVICE_ID_INTEL_Q35_AHCI (0x2922)
34 #define PCI_MSI_FLAGS_RESERVED (0xFF00)
35 #define PCI_PM_CTRL_RESERVED (0xFC)
37 #define PCI_PI(REG32) (((REG32) >> 8) & 0xFF)
38 #define PCI_SCC(REG32) (((REG32) >> 16) & 0xFF)
45 #define AHCI_CAP (0)
46 #define AHCI_CAP_NP (0x1F)
47 #define AHCI_CAP_SXS (0x20)
48 #define AHCI_CAP_EMS (0x40)
49 #define AHCI_CAP_CCCS (0x80)
[all …]
/qemu/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc32 { "MMID", 89, 0 },
33 { "DDR", 104, 0 },
34 { "CONFIGID0", 176, 0 },
35 { "CONFIGID1", 208, 0 },
36 { "INTERRUPT", 226, 0 },
37 { "INTCLEAR", 227, 0 },
38 { "CCOUNT", 234, 0 },
39 { "PRID", 235, 0 },
40 { "ICOUNT", 236, 0 },
41 { "CCOMPARE0", 240, 0 },
[all …]
/qemu/hw/display/
H A Dtcx.c39 #define FCODE_MAX_ROM_SIZE 0x10000
44 #define TCX_THC_NREGS 0x1000
45 #define TCX_DHC_NREGS 0x4000
46 #define TCX_TEC_NREGS 0x1000
47 #define TCX_ALT_NREGS 0x8000
48 #define TCX_STIP_NREGS 0x800000
49 #define TCX_BLIT_NREGS 0x800000
50 #define TCX_RSTIP_NREGS 0x800000
51 #define TCX_RBLIT_NREGS 0x800000
53 #define TCX_THC_MISC 0x818
[all …]
/qemu/hw/riscv/
H A Dspike.c9 * 0) HTIF Console and Poweroff
45 [SPIKE_MROM] = { 0x1000, 0xf000 },
46 [SPIKE_HTIF] = { 0x1000000, 0x1000 },
47 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
48 [SPIKE_DRAM] = { 0x80000000, 0x0 },
76 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
77 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); in create_fdt()
83 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); in create_fdt()
87 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); in create_fdt()
89 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); in create_fdt()
[all …]
/qemu/target/xtensa/core-dc233c/
H A Dxtensa-modules.c.inc3 Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc.
32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]
/qemu/target/xtensa/core-de212/
H A Dxtensa-modules.c.inc32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
41 { "MMID", 89, 0 },
[all …]
/qemu/target/xtensa/core-dc232b/
H A Dxtensa-modules.c.inc29 { "LBEG", 0, 0 },
30 { "LEND", 1, 0 },
31 { "LCOUNT", 2, 0 },
32 { "ACCLO", 16, 0 },
33 { "ACCHI", 17, 0 },
34 { "M0", 32, 0 },
35 { "M1", 33, 0 },
36 { "M2", 34, 0 },
37 { "M3", 35, 0 },
38 { "PTEVADDR", 83, 0 },
[all …]
/qemu/target/sh4/
H A Dtranslate.c98 for (i = 0; i < 24; i++) { in sh4_translate_init()
154 for (i = 0; i < 32; i++) in sh4_translate_init()
165 qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", in superh_cpu_dump_state()
167 qemu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", in superh_cpu_dump_state()
169 qemu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", in superh_cpu_dump_state()
171 for (i = 0; i < 24; i += 4) { in superh_cpu_dump_state()
172 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", in superh_cpu_dump_state()
177 qemu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
180 qemu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
183 qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
[all …]

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