Lines Matching +full:0 +full:xf000
33 #define PCI_DEVICE_ID_INTEL_Q35_AHCI (0x2922)
34 #define PCI_MSI_FLAGS_RESERVED (0xFF00)
35 #define PCI_PM_CTRL_RESERVED (0xFC)
37 #define PCI_PI(REG32) (((REG32) >> 8) & 0xFF)
38 #define PCI_SCC(REG32) (((REG32) >> 16) & 0xFF)
45 #define AHCI_CAP (0)
46 #define AHCI_CAP_NP (0x1F)
47 #define AHCI_CAP_SXS (0x20)
48 #define AHCI_CAP_EMS (0x40)
49 #define AHCI_CAP_CCCS (0x80)
50 #define AHCI_CAP_NCS (0x1F00)
51 #define AHCI_CAP_PSC (0x2000)
52 #define AHCI_CAP_SSC (0x4000)
53 #define AHCI_CAP_PMD (0x8000)
54 #define AHCI_CAP_FBSS (0x10000)
55 #define AHCI_CAP_SPM (0x20000)
56 #define AHCI_CAP_SAM (0x40000)
57 #define AHCI_CAP_RESERVED (0x80000)
58 #define AHCI_CAP_ISS (0xF00000)
59 #define AHCI_CAP_SCLO (0x1000000)
60 #define AHCI_CAP_SAL (0x2000000)
61 #define AHCI_CAP_SALP (0x4000000)
62 #define AHCI_CAP_SSS (0x8000000)
63 #define AHCI_CAP_SMPS (0x10000000)
64 #define AHCI_CAP_SSNTF (0x20000000)
65 #define AHCI_CAP_SNCQ (0x40000000)
66 #define AHCI_CAP_S64A (0x80000000)
69 #define AHCI_GHC_HR (0x01)
70 #define AHCI_GHC_IE (0x02)
71 #define AHCI_GHC_MRSM (0x04)
72 #define AHCI_GHC_RESERVED (0x7FFFFFF8)
73 #define AHCI_GHC_AE (0x80000000)
80 #define AHCI_CCCCTL_EN (0x01)
81 #define AHCI_CCCCTL_RESERVED (0x06)
82 #define AHCI_CCCCTL_CC (0xFF00)
83 #define AHCI_CCCCTL_TV (0xFFFF0000)
89 #define AHCI_EMCTL_STSMR (0x01)
90 #define AHCI_EMCTL_CTLTM (0x100)
91 #define AHCI_EMCTL_CTLRST (0x200)
92 #define AHCI_EMCTL_RESERVED (0xF0F0FCFE)
95 #define AHCI_CAP2_BOH (0x01)
96 #define AHCI_CAP2_NVMP (0x02)
97 #define AHCI_CAP2_APST (0x04)
98 #define AHCI_CAP2_RESERVED (0xFFFFFFF8)
107 #define AHCI_PX_CLB (0)
108 #define AHCI_PX_CLB_RESERVED (0x1FF)
113 #define AHCI_PX_FB_RESERVED (0xFF)
118 #define AHCI_PX_IS_DHRS (0x1)
119 #define AHCI_PX_IS_PSS (0x2)
120 #define AHCI_PX_IS_DSS (0x4)
121 #define AHCI_PX_IS_SDBS (0x8)
122 #define AHCI_PX_IS_UFS (0x10)
123 #define AHCI_PX_IS_DPS (0x20)
124 #define AHCI_PX_IS_PCS (0x40)
125 #define AHCI_PX_IS_DMPS (0x80)
126 #define AHCI_PX_IS_RESERVED (0x23FFF00)
127 #define AHCI_PX_IS_PRCS (0x400000)
128 #define AHCI_PX_IS_IPMS (0x800000)
129 #define AHCI_PX_IS_OFS (0x1000000)
130 #define AHCI_PX_IS_INFS (0x4000000)
131 #define AHCI_PX_IS_IFS (0x8000000)
132 #define AHCI_PX_IS_HBDS (0x10000000)
133 #define AHCI_PX_IS_HBFS (0x20000000)
134 #define AHCI_PX_IS_TFES (0x40000000)
135 #define AHCI_PX_IS_CPDS (0x80000000)
138 #define AHCI_PX_IE_DHRE (0x1)
139 #define AHCI_PX_IE_PSE (0x2)
140 #define AHCI_PX_IE_DSE (0x4)
141 #define AHCI_PX_IE_SDBE (0x8)
142 #define AHCI_PX_IE_UFE (0x10)
143 #define AHCI_PX_IE_DPE (0x20)
144 #define AHCI_PX_IE_PCE (0x40)
145 #define AHCI_PX_IE_DMPE (0x80)
146 #define AHCI_PX_IE_RESERVED (0x23FFF00)
147 #define AHCI_PX_IE_PRCE (0x400000)
148 #define AHCI_PX_IE_IPME (0x800000)
149 #define AHCI_PX_IE_OFE (0x1000000)
150 #define AHCI_PX_IE_INFE (0x4000000)
151 #define AHCI_PX_IE_IFE (0x8000000)
152 #define AHCI_PX_IE_HBDE (0x10000000)
153 #define AHCI_PX_IE_HBFE (0x20000000)
154 #define AHCI_PX_IE_TFEE (0x40000000)
155 #define AHCI_PX_IE_CPDE (0x80000000)
158 #define AHCI_PX_CMD_ST (0x1)
159 #define AHCI_PX_CMD_SUD (0x2)
160 #define AHCI_PX_CMD_POD (0x4)
161 #define AHCI_PX_CMD_CLO (0x8)
162 #define AHCI_PX_CMD_FRE (0x10)
163 #define AHCI_PX_CMD_RESERVED (0xE0)
164 #define AHCI_PX_CMD_CCS (0x1F00)
165 #define AHCI_PX_CMD_MPSS (0x2000)
166 #define AHCI_PX_CMD_FR (0x4000)
167 #define AHCI_PX_CMD_CR (0x8000)
168 #define AHCI_PX_CMD_CPS (0x10000)
169 #define AHCI_PX_CMD_PMA (0x20000)
170 #define AHCI_PX_CMD_HPCP (0x40000)
171 #define AHCI_PX_CMD_MPSP (0x80000)
172 #define AHCI_PX_CMD_CPD (0x100000)
173 #define AHCI_PX_CMD_ESP (0x200000)
174 #define AHCI_PX_CMD_FBSCP (0x400000)
175 #define AHCI_PX_CMD_APSTE (0x800000)
176 #define AHCI_PX_CMD_ATAPI (0x1000000)
177 #define AHCI_PX_CMD_DLAE (0x2000000)
178 #define AHCI_PX_CMD_ALPE (0x4000000)
179 #define AHCI_PX_CMD_ASP (0x8000000)
180 #define AHCI_PX_CMD_ICC (0xF0000000)
185 #define AHCI_PX_TFD_STS (0xFF)
186 #define AHCI_PX_TFD_STS_ERR (0x01)
187 #define AHCI_PX_TFD_STS_CS1 (0x06)
188 #define AHCI_PX_TFD_STS_DRQ (0x08)
189 #define AHCI_PX_TFD_STS_CS2 (0x70)
190 #define AHCI_PX_TFD_STS_BSY (0x80)
191 #define AHCI_PX_TFD_ERR (0xFF00)
192 #define AHCI_PX_TFD_RESERVED (0xFFFF0000)
195 #define AHCI_PX_SIG_SECTOR_COUNT (0xFF)
196 #define AHCI_PX_SIG_LBA_LOW (0xFF00)
197 #define AHCI_PX_SIG_LBA_MID (0xFF0000)
198 #define AHCI_PX_SIG_LBA_HIGH (0xFF000000)
201 #define AHCI_PX_SSTS_DET (0x0F)
202 #define AHCI_PX_SSTS_SPD (0xF0)
203 #define AHCI_PX_SSTS_IPM (0xF00)
204 #define AHCI_PX_SSTS_RESERVED (0xFFFFF000)
205 #define SSTS_DET_NO_DEVICE (0x00)
206 #define SSTS_DET_PRESENT (0x01)
207 #define SSTS_DET_ESTABLISHED (0x03)
208 #define SSTS_DET_OFFLINE (0x04)
213 #define AHCI_PX_SERR_ERR (0xFFFF)
214 #define AHCI_PX_SERR_DIAG (0xFFFF0000)
215 #define AHCI_PX_SERR_DIAG_X (0x04000000)
222 #define AHCI_PX_FBS_EN (0x1)
223 #define AHCI_PX_FBS_DEC (0x2)
224 #define AHCI_PX_FBS_SDE (0x4)
225 #define AHCI_PX_FBS_DEV (0xF00)
226 #define AHCI_PX_FBS_ADO (0xF000)
227 #define AHCI_PX_FBS_DWE (0xF0000)
228 #define AHCI_PX_FBS_RESERVED (0xFFF000F8)
237 #define AHCI_VERSION_0_95 (0x00000905)
238 #define AHCI_VERSION_1_0 (0x00010000)
239 #define AHCI_VERSION_1_1 (0x00010100)
240 #define AHCI_VERSION_1_2 (0x00010200)
241 #define AHCI_VERSION_1_3 (0x00010300)
246 #define AHCI_SIGNATURE_CDROM (0xeb140101)
247 #define AHCI_SIGNATURE_DISK (0x00000101)
251 REG_H2D_FIS = 0x27,
252 REG_D2H_FIS = 0x34,
253 DMA_ACTIVATE_FIS = 0x39,
254 DMA_SETUP_FIS = 0x41,
255 DATA_FIS = 0x46,
256 BIST_ACTIVATE_FIS = 0x58,
257 PIO_SETUP_FIS = 0x5F,
258 SDB_FIS = 0xA1
262 #define REG_H2D_FIS_CMD 0x80
267 CMD_READ_DMA = 0xC8,
268 CMD_READ_DMA_EXT = 0x25,
269 CMD_WRITE_DMA = 0xCA,
270 CMD_WRITE_DMA_EXT = 0x35,
272 CMD_READ_PIO = 0x20,
273 CMD_READ_PIO_EXT = 0x24,
274 CMD_WRITE_PIO = 0x30,
275 CMD_WRITE_PIO_EXT = 0x34,
277 CMD_READ_MAX = 0xF8,
278 CMD_READ_MAX_EXT = 0x27,
279 CMD_FLUSH_CACHE = 0xE7,
280 CMD_IDENTIFY = 0xEC,
281 CMD_PACKET = 0xA0,
282 CMD_PACKET_ID = 0xA1,
284 READ_FPDMA_QUEUED = 0x60,
285 WRITE_FPDMA_QUEUED = 0x61,
290 CMD_ATAPI_TEST_UNIT_READY = 0x00,
291 CMD_ATAPI_REQUEST_SENSE = 0x03,
292 CMD_ATAPI_START_STOP_UNIT = 0x1b,
293 CMD_ATAPI_READ_10 = 0x28,
294 CMD_ATAPI_READ_CD = 0xbe,
298 SENSE_NO_SENSE = 0x00,
299 SENSE_NOT_READY = 0x02,
300 SENSE_UNIT_ATTENTION = 0x06,
304 ASC_MEDIUM_MAY_HAVE_CHANGED = 0x28,
305 ASC_MEDIUM_NOT_PRESENT = 0x3a,
309 #define CMDH_CFL (0x1F)
310 #define CMDH_ATAPI (0x20)
311 #define CMDH_WRITE (0x40)
312 #define CMDH_PREFETCH (0x80)
313 #define CMDH_RESET (0x100)
314 #define CMDH_BIST (0x200)
315 #define CMDH_CLR_BSY (0x400)
316 #define CMDH_RES (0x800)
317 #define CMDH_PMP (0xF000)
320 #define ATA_DEVICE_MAGIC 0xA0 /* used in ata1-3 */
321 #define ATA_DEVICE_LBA 0x40
322 #define NCQ_DEVICE_MAGIC 0x40 /* for ncq device registers */
323 #define ATA_DEVICE_DRIVE 0x10
324 #define ATA_DEVICE_HEAD 0x0F
437 uint8_t sector_low; /* H2D: Feature 7:0 */
445 uint8_t tag; /* H2D: Count 0:7 */
472 uint32_t dbc; /* Data Byte Count (0-indexed) & Interrupt Flag (bit 2^31) */
496 #define BITANY(data, mask) (((data) & (mask)) != 0)
498 #define BITCLR(data, mask) (((data) & (mask)) == 0)
500 #define ASSERT_BIT_CLEAR(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
503 #define CMD_TBL_SIZ(n) ((0x80 + ((n) * sizeof(PRD)) + 0x7F) & ~0x7F)