| /linux-5.10/drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_cfg.c | 22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
|
| /linux-5.10/Documentation/devicetree/bindings/interconnect/ |
| D | qcom,msm8974.yaml | 56 reg = <0xfc380000 0x6a000>;
|
| /linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_catalog.c | 46 #define INTF_SDM845_MASK (0)
69 .max_mixer_blendstages = 0xb,
85 .max_mixer_blendstages = 0x9,
97 .max_mixer_blendstages = 0xb,
113 .max_mixer_blendstages = 0xb,
129 .base = 0x0, .len = 0x45C,
130 .features = 0,
131 .highest_bank_bit = 0x2,
133 .reg_off = 0x2AC, .bit_off = 0},
135 .reg_off = 0x2B4, .bit_off = 0},
[all …]
|
| D | dpu_hw_interrupts.c | 17 #define MDP_SSPP_TOP0_OFF 0x0
18 #define MDP_INTF_0_OFF 0x6A000
19 #define MDP_INTF_1_OFF 0x6A800
20 #define MDP_INTF_2_OFF 0x6B000
21 #define MDP_INTF_3_OFF 0x6B800
22 #define MDP_INTF_4_OFF 0x6C000
23 #define MDP_AD4_0_OFF 0x7C000
24 #define MDP_AD4_1_OFF 0x7D000
25 #define MDP_AD4_INTR_EN_OFF 0x41c
26 #define MDP_AD4_INTR_CLEAR_OFF 0x424
[all …]
|
| /linux-5.10/drivers/rapidio/devices/ |
| D | tsi721.h | 13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
|
| /linux-5.10/arch/arm/boot/dts/ |
| D | qcom-msm8974.dtsi | 25 reg = <0x08000000 0x5100000>;
30 reg = <0x0d100000 0x100000>;
35 reg = <0x0d200000 0xa00000>;
40 reg = <0x0dc00000 0x1900000>;
45 reg = <0x0f500000 0x500000>;
50 reg = <0xfa00000 0x200000>;
55 reg = <0x0fc00000 0x160000>;
60 reg = <0x0fd60000 0x20000>;
66 reg = <0x0fd80000 0x180000>;
75 #size-cells = <0>;
[all …]
|
| D | omap5-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
10 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
11 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
12 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
13 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
14 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
[all …]
|
| D | omap4-l4.dtsi | 2 &l4_cfg { /* 0x4a000000 */
4 reg = <0x4a000000 0x800>,
5 <0x4a000800 0x800>,
6 <0x4a001000 0x1000>;
10 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
11 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
12 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
13 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
14 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
15 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
[all …]
|
| D | dra7-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
13 segment@0 { /* 0x4a000000 */
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
[all …]
|
| /linux-5.10/drivers/clk/qcom/ |
| D | gcc-sdm660.c | 41 { P_XO, 0 },
53 { P_XO, 0 },
63 { P_XO, 0 },
77 { P_XO, 0 },
87 { P_XO, 0 },
97 { P_XO, 0 },
115 { P_XO, 0 },
129 { P_XO, 0 },
154 .offset = 0x0,
157 .enable_reg = 0x52000,
[all …]
|
| D | gcc-sc7180.c | 37 .offset = 0x0,
40 .enable_reg = 0x52010,
41 .enable_mask = BIT(0),
55 { 0x1, 2 },
60 .offset = 0x0,
90 .offset = 0x01000,
93 .enable_reg = 0x52010,
108 .offset = 0x76000,
111 .enable_reg = 0x52010,
126 .offset = 0x13000,
[all …]
|
| D | gcc-msm8998.c | 39 { P_XO, 0 },
53 { P_XO, 0 },
65 { P_XO, 0 },
81 { P_XO, 0 },
93 { P_XO, 0 },
107 { P_XO, 0 },
132 { 250000000, 2000000000, 0 },
137 .offset = 0x0,
142 .enable_reg = 0x52000,
143 .enable_mask = BIT(0),
[all …]
|
| D | gcc-msm8916.c | 46 { P_XO, 0 },
56 { P_XO, 0 },
68 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
104 { P_XO, 0 },
118 { P_XO, 0 },
130 { P_XO, 0, },
140 { P_XO, 0 },
152 { P_XO, 0 },
[all …]
|
| D | gcc-sm8250.c | 37 .offset = 0x0,
40 .enable_reg = 0x52018,
41 .enable_mask = BIT(0),
54 { 0x1, 2 },
59 .offset = 0x0,
76 .offset = 0x76000,
79 .enable_reg = 0x52018,
93 .offset = 0x1c000,
96 .enable_reg = 0x52018,
110 { P_BI_TCXO, 0 },
[all …]
|
| D | gcc-sdm845.c | 39 { P_BI_TCXO, 0 },
53 { P_BI_TCXO, 0 },
69 { P_BI_TCXO, 0 },
81 { P_BI_TCXO, 0 },
93 { P_BI_TCXO, 0 },
103 { P_BI_TCXO, 0 },
138 { P_BI_TCXO, 0 },
154 .offset = 0x0,
157 .enable_reg = 0x52000,
158 .enable_mask = BIT(0),
[all …]
|
| D | gcc-msm8996.c | 50 { P_XO, 0 },
60 { P_XO, 0 },
70 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
106 { P_XO, 0 },
120 { P_XO, 0 },
134 { P_XO, 0 },
152 { P_XO, 0 },
183 .offset = 0x00000,
[all …]
|
| D | gcc-sm8150.c | 38 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
64 .offset = 0x0,
81 .offset = 0x1a000,
84 .enable_reg = 0x52000,
[all …]
|
| D | gcc-msm8939.c | 54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
[all …]
|
| D | gcc-ipq8074.c | 58 { P_XO, 0 },
69 { P_XO, 0 },
81 { P_XO, 0 },
94 { P_XO, 0 },
107 { P_XO, 0 },
120 { P_XO, 0 },
131 { P_USB3PHY_0_PIPE, 0 },
141 { P_USB3PHY_1_PIPE, 0 },
151 { P_PCIE20_PHY0_PIPE, 0 },
161 { P_PCIE20_PHY1_PIPE, 0 },
[all …]
|
| D | gcc-ipq6018.c | 53 .offset = 0x21000,
56 .enable_reg = 0x0b000,
57 .enable_mask = BIT(0),
83 .offset = 0x21000,
103 { P_XO, 0 },
109 .offset = 0x25000,
113 .enable_reg = 0x0b000,
127 .offset = 0x25000,
141 .offset = 0x37000,
144 .enable_reg = 0x0b000,
[all …]
|