Lines Matching +full:0 +full:x6a000
38 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
64 .offset = 0x0,
81 .offset = 0x1a000,
84 .enable_reg = 0x52000,
99 .offset = 0x1c000,
102 .enable_reg = 0x52000,
117 { P_BI_TCXO, 0 },
131 { P_BI_TCXO, 0 },
147 { P_BI_TCXO, 0 },
159 { P_BI_TCXO, 0 },
171 { P_BI_TCXO, 0 },
181 { P_BI_TCXO, 0 },
197 { P_BI_TCXO, 0 },
213 { P_BI_TCXO, 0 },
229 F(19200000, P_BI_TCXO, 1, 0, 0),
230 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
231 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
236 .cmd_rcgr = 0x48014,
237 .mnd_width = 0,
251 F(19200000, P_BI_TCXO, 1, 0, 0),
252 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
253 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
254 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
259 .cmd_rcgr = 0x6038,
260 .mnd_width = 0,
276 F(19200000, P_BI_TCXO, 1, 0, 0),
277 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
278 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
279 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
280 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
285 .cmd_rcgr = 0x601c,
300 F(19200000, P_BI_TCXO, 1, 0, 0),
301 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
302 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
303 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
304 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
309 .cmd_rcgr = 0x64004,
324 .cmd_rcgr = 0x65004,
339 .cmd_rcgr = 0x66004,
354 F(9600000, P_BI_TCXO, 2, 0, 0),
355 F(19200000, P_BI_TCXO, 1, 0, 0),
360 .cmd_rcgr = 0x6b02c,
375 .cmd_rcgr = 0x8d02c,
390 F(19200000, P_BI_TCXO, 1, 0, 0),
391 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
396 .cmd_rcgr = 0x6f014,
397 .mnd_width = 0,
411 F(9600000, P_BI_TCXO, 2, 0, 0),
412 F(19200000, P_BI_TCXO, 1, 0, 0),
413 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
418 .cmd_rcgr = 0x33010,
419 .mnd_width = 0,
433 F(19200000, P_BI_TCXO, 1, 0, 0),
434 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
435 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
436 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
441 .cmd_rcgr = 0x4b008,
442 .mnd_width = 0,
458 F(19200000, P_BI_TCXO, 1, 0, 0),
465 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
469 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
475 .cmd_rcgr = 0x17148,
490 .cmd_rcgr = 0x17278,
505 .cmd_rcgr = 0x173a8,
520 .cmd_rcgr = 0x174d8,
535 .cmd_rcgr = 0x17608,
550 .cmd_rcgr = 0x17738,
565 .cmd_rcgr = 0x17868,
580 .cmd_rcgr = 0x17998,
595 .cmd_rcgr = 0x18148,
610 .cmd_rcgr = 0x18278,
625 .cmd_rcgr = 0x183a8,
640 .cmd_rcgr = 0x184d8,
655 .cmd_rcgr = 0x18608,
670 .cmd_rcgr = 0x18738,
685 .cmd_rcgr = 0x1e148,
700 .cmd_rcgr = 0x1e278,
715 .cmd_rcgr = 0x1e3a8,
730 .cmd_rcgr = 0x1e4d8,
745 .cmd_rcgr = 0x1e608,
760 .cmd_rcgr = 0x1e738,
776 F(9600000, P_BI_TCXO, 2, 0, 0),
777 F(19200000, P_BI_TCXO, 1, 0, 0),
779 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
780 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
781 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
786 .cmd_rcgr = 0x1400c,
802 F(9600000, P_BI_TCXO, 2, 0, 0),
803 F(19200000, P_BI_TCXO, 1, 0, 0),
805 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
806 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
811 .cmd_rcgr = 0x1600c,
831 .cmd_rcgr = 0x36010,
846 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
847 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
848 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
849 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
850 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
855 .cmd_rcgr = 0x75020,
870 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
871 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
872 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
873 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
878 .cmd_rcgr = 0x75060,
879 .mnd_width = 0,
893 F(19200000, P_BI_TCXO, 1, 0, 0),
898 .cmd_rcgr = 0x75094,
899 .mnd_width = 0,
913 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
914 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
915 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
920 .cmd_rcgr = 0x75078,
921 .mnd_width = 0,
935 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
936 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
937 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
938 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
939 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
944 .cmd_rcgr = 0x77020,
959 .cmd_rcgr = 0x77060,
960 .mnd_width = 0,
974 .cmd_rcgr = 0x77094,
975 .mnd_width = 0,
989 .cmd_rcgr = 0x77078,
990 .mnd_width = 0,
1004 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1005 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1006 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1007 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1008 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1013 .cmd_rcgr = 0xf01c,
1028 F(19200000, P_BI_TCXO, 1, 0, 0),
1029 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1030 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1035 .cmd_rcgr = 0xf034,
1036 .mnd_width = 0,
1050 .cmd_rcgr = 0x1001c,
1065 .cmd_rcgr = 0x10034,
1066 .mnd_width = 0,
1080 .cmd_rcgr = 0xf060,
1081 .mnd_width = 0,
1095 .cmd_rcgr = 0x10060,
1096 .mnd_width = 0,
1110 .halt_reg = 0x90018,
1113 .enable_reg = 0x90018,
1114 .enable_mask = BIT(0),
1123 .halt_reg = 0x750c0,
1125 .hwcg_reg = 0x750c0,
1128 .enable_reg = 0x750c0,
1129 .enable_mask = BIT(0),
1142 .halt_reg = 0x750c0,
1144 .hwcg_reg = 0x750c0,
1147 .enable_reg = 0x750c0,
1161 .halt_reg = 0x770c0,
1163 .hwcg_reg = 0x770c0,
1166 .enable_reg = 0x770c0,
1167 .enable_mask = BIT(0),
1180 .halt_reg = 0x770c0,
1182 .hwcg_reg = 0x770c0,
1185 .enable_reg = 0x770c0,
1199 .halt_reg = 0xf07c,
1202 .enable_reg = 0xf07c,
1203 .enable_mask = BIT(0),
1216 .halt_reg = 0x1007c,
1219 .enable_reg = 0x1007c,
1220 .enable_mask = BIT(0),
1233 .halt_reg = 0x38004,
1235 .hwcg_reg = 0x38004,
1238 .enable_reg = 0x52004,
1252 .halt_reg = 0xb008,
1254 .hwcg_reg = 0xb008,
1257 .enable_reg = 0xb008,
1258 .enable_mask = BIT(0),
1268 .halt_reg = 0xb030,
1271 .enable_reg = 0xb030,
1272 .enable_mask = BIT(0),
1281 .halt_reg = 0xb034,
1284 .enable_reg = 0xb034,
1285 .enable_mask = BIT(0),
1295 .halt_reg = 0xb044,
1298 .enable_reg = 0xb044,
1299 .enable_mask = BIT(0),
1309 .halt_reg = 0xf078,
1312 .enable_reg = 0xf078,
1313 .enable_mask = BIT(0),
1326 .halt_reg = 0x10078,
1329 .enable_reg = 0x10078,
1330 .enable_mask = BIT(0),
1343 .halt_reg = 0x48000,
1346 .enable_reg = 0x52004,
1361 .halt_reg = 0x48190,
1364 .enable_reg = 0x48190,
1365 .enable_mask = BIT(0),
1376 .halt_reg = 0x48004,
1378 .hwcg_reg = 0x48004,
1381 .enable_reg = 0x52004,
1393 .halt_reg = 0x48008,
1396 .enable_reg = 0x48008,
1397 .enable_mask = BIT(0),
1406 .halt_reg = 0x71154,
1409 .enable_reg = 0x71154,
1410 .enable_mask = BIT(0),
1423 .halt_reg = 0xb00c,
1425 .hwcg_reg = 0xb00c,
1428 .enable_reg = 0xb00c,
1429 .enable_mask = BIT(0),
1439 .halt_reg = 0xb038,
1442 .enable_reg = 0xb038,
1443 .enable_mask = BIT(0),
1452 .halt_reg = 0xb03c,
1455 .enable_reg = 0xb03c,
1456 .enable_mask = BIT(0),
1466 .halt_reg = 0xb048,
1469 .enable_reg = 0xb048,
1470 .enable_mask = BIT(0),
1480 .halt_reg = 0x6010,
1483 .enable_reg = 0x6010,
1484 .enable_mask = BIT(0),
1493 .halt_reg = 0x6034,
1496 .enable_reg = 0x6034,
1497 .enable_mask = BIT(0),
1510 .halt_reg = 0x6018,
1513 .enable_reg = 0x6018,
1514 .enable_mask = BIT(0),
1527 .halt_reg = 0x6014,
1529 .hwcg_reg = 0x6014,
1532 .enable_reg = 0x6014,
1533 .enable_mask = BIT(0),
1542 .halt_reg = 0x64000,
1545 .enable_reg = 0x64000,
1546 .enable_mask = BIT(0),
1559 .halt_reg = 0x65000,
1562 .enable_reg = 0x65000,
1563 .enable_mask = BIT(0),
1576 .halt_reg = 0x66000,
1579 .enable_reg = 0x66000,
1580 .enable_mask = BIT(0),
1593 .halt_reg = 0x71004,
1595 .hwcg_reg = 0x71004,
1598 .enable_reg = 0x71004,
1599 .enable_mask = BIT(0),
1612 .enable_reg = 0x52004,
1628 .enable_reg = 0x52004,
1642 .halt_reg = 0x8c010,
1645 .enable_reg = 0x8c010,
1646 .enable_mask = BIT(0),
1655 .halt_reg = 0x7100c,
1658 .enable_reg = 0x7100c,
1659 .enable_mask = BIT(0),
1668 .halt_reg = 0x71018,
1671 .enable_reg = 0x71018,
1672 .enable_mask = BIT(0),
1681 .halt_reg = 0x4d010,
1684 .enable_reg = 0x4d010,
1685 .enable_mask = BIT(0),
1694 .halt_reg = 0x4d008,
1697 .enable_reg = 0x4d008,
1698 .enable_mask = BIT(0),
1707 .halt_reg = 0x4d004,
1709 .hwcg_reg = 0x4d004,
1712 .enable_reg = 0x4d004,
1713 .enable_mask = BIT(0),
1726 .enable_reg = 0x52004,
1742 .enable_reg = 0x52004,
1756 .halt_reg = 0x4d00c,
1759 .enable_reg = 0x4d00c,
1760 .enable_mask = BIT(0),
1769 .halt_reg = 0x6f02c,
1772 .enable_reg = 0x6f02c,
1773 .enable_mask = BIT(0),
1786 .halt_reg = 0x6f030,
1789 .enable_reg = 0x6f030,
1790 .enable_mask = BIT(0),
1803 .halt_reg = 0x6b020,
1806 .enable_reg = 0x5200c,
1820 .halt_reg = 0x6b01c,
1822 .hwcg_reg = 0x6b01c,
1825 .enable_reg = 0x5200c,
1835 .halt_reg = 0x8c00c,
1838 .enable_reg = 0x8c00c,
1839 .enable_mask = BIT(0),
1848 .halt_reg = 0x6b018,
1851 .enable_reg = 0x5200c,
1862 .halt_reg = 0x6b024,
1865 .enable_reg = 0x5200c,
1875 .halt_reg = 0x6b014,
1877 .hwcg_reg = 0x6b014,
1880 .enable_reg = 0x5200c,
1881 .enable_mask = BIT(0),
1890 .halt_reg = 0x6b010,
1893 .enable_reg = 0x5200c,
1903 .halt_reg = 0x8d020,
1906 .enable_reg = 0x52004,
1920 .halt_reg = 0x8d01c,
1922 .hwcg_reg = 0x8d01c,
1925 .enable_reg = 0x52004,
1935 .halt_reg = 0x8c02c,
1938 .enable_reg = 0x8c02c,
1939 .enable_mask = BIT(0),
1948 .halt_reg = 0x8d018,
1951 .enable_reg = 0x52004,
1962 .halt_reg = 0x8d024,
1965 .enable_reg = 0x52004,
1975 .halt_reg = 0x8d014,
1977 .hwcg_reg = 0x8d014,
1980 .enable_reg = 0x52004,
1990 .halt_reg = 0x8d010,
1993 .enable_reg = 0x52004,
2003 .halt_reg = 0x6f004,
2006 .enable_reg = 0x6f004,
2007 .enable_mask = BIT(0),
2020 .halt_reg = 0x3300c,
2023 .enable_reg = 0x3300c,
2024 .enable_mask = BIT(0),
2037 .halt_reg = 0x33004,
2039 .hwcg_reg = 0x33004,
2042 .enable_reg = 0x33004,
2043 .enable_mask = BIT(0),
2052 .halt_reg = 0x33008,
2055 .enable_reg = 0x33008,
2056 .enable_mask = BIT(0),
2065 .halt_reg = 0x34004,
2068 .enable_reg = 0x52004,
2078 .halt_reg = 0xb018,
2080 .hwcg_reg = 0xb018,
2083 .enable_reg = 0xb018,
2084 .enable_mask = BIT(0),
2093 .halt_reg = 0xb01c,
2095 .hwcg_reg = 0xb01c,
2098 .enable_reg = 0xb01c,
2099 .enable_mask = BIT(0),
2108 .halt_reg = 0xb020,
2110 .hwcg_reg = 0xb020,
2113 .enable_reg = 0xb020,
2114 .enable_mask = BIT(0),
2123 .halt_reg = 0xb010,
2125 .hwcg_reg = 0xb010,
2128 .enable_reg = 0xb010,
2129 .enable_mask = BIT(0),
2138 .halt_reg = 0xb014,
2140 .hwcg_reg = 0xb014,
2143 .enable_reg = 0xb014,
2144 .enable_mask = BIT(0),
2153 .halt_reg = 0x4b000,
2156 .enable_reg = 0x4b000,
2157 .enable_mask = BIT(0),
2166 .halt_reg = 0x4b004,
2169 .enable_reg = 0x4b004,
2170 .enable_mask = BIT(0),
2183 .halt_reg = 0x17144,
2186 .enable_reg = 0x5200c,
2200 .halt_reg = 0x17274,
2203 .enable_reg = 0x5200c,
2217 .halt_reg = 0x173a4,
2220 .enable_reg = 0x5200c,
2234 .halt_reg = 0x174d4,
2237 .enable_reg = 0x5200c,
2251 .halt_reg = 0x17604,
2254 .enable_reg = 0x5200c,
2268 .halt_reg = 0x17734,
2271 .enable_reg = 0x5200c,
2285 .halt_reg = 0x17864,
2288 .enable_reg = 0x5200c,
2302 .halt_reg = 0x17994,
2305 .enable_reg = 0x5200c,
2319 .halt_reg = 0x18144,
2322 .enable_reg = 0x5200c,
2336 .halt_reg = 0x18274,
2339 .enable_reg = 0x5200c,
2353 .halt_reg = 0x183a4,
2356 .enable_reg = 0x5200c,
2370 .halt_reg = 0x184d4,
2373 .enable_reg = 0x5200c,
2387 .halt_reg = 0x18604,
2390 .enable_reg = 0x5200c,
2404 .halt_reg = 0x18734,
2407 .enable_reg = 0x5200c,
2421 .halt_reg = 0x1e144,
2424 .enable_reg = 0x52014,
2438 .halt_reg = 0x1e274,
2441 .enable_reg = 0x52014,
2455 .halt_reg = 0x1e3a4,
2458 .enable_reg = 0x52014,
2472 .halt_reg = 0x1e4d4,
2475 .enable_reg = 0x52014,
2489 .halt_reg = 0x1e604,
2492 .enable_reg = 0x52014,
2506 .halt_reg = 0x1e734,
2509 .enable_reg = 0x52014,
2523 .halt_reg = 0x17004,
2526 .enable_reg = 0x5200c,
2536 .halt_reg = 0x17008,
2538 .hwcg_reg = 0x17008,
2541 .enable_reg = 0x5200c,
2551 .halt_reg = 0x18004,
2554 .enable_reg = 0x5200c,
2564 .halt_reg = 0x18008,
2566 .hwcg_reg = 0x18008,
2569 .enable_reg = 0x5200c,
2579 .halt_reg = 0x1e004,
2582 .enable_reg = 0x52014,
2592 .halt_reg = 0x1e008,
2594 .hwcg_reg = 0x1e008,
2597 .enable_reg = 0x52014,
2607 .halt_reg = 0x14008,
2610 .enable_reg = 0x14008,
2611 .enable_mask = BIT(0),
2620 .halt_reg = 0x14004,
2623 .enable_reg = 0x14004,
2624 .enable_mask = BIT(0),
2637 .halt_reg = 0x16008,
2640 .enable_reg = 0x16008,
2641 .enable_mask = BIT(0),
2650 .halt_reg = 0x16004,
2653 .enable_reg = 0x16004,
2654 .enable_mask = BIT(0),
2667 .halt_reg = 0x4819c,
2670 .enable_reg = 0x52004,
2671 .enable_mask = BIT(0),
2685 .halt_reg = 0x36004,
2688 .enable_reg = 0x36004,
2689 .enable_mask = BIT(0),
2698 .halt_reg = 0x3600c,
2701 .enable_reg = 0x3600c,
2702 .enable_mask = BIT(0),
2711 .halt_reg = 0x36008,
2714 .enable_reg = 0x36008,
2715 .enable_mask = BIT(0),
2728 .halt_reg = 0x75014,
2730 .hwcg_reg = 0x75014,
2733 .enable_reg = 0x75014,
2734 .enable_mask = BIT(0),
2743 .halt_reg = 0x75010,
2745 .hwcg_reg = 0x75010,
2748 .enable_reg = 0x75010,
2749 .enable_mask = BIT(0),
2762 .halt_reg = 0x75010,
2764 .hwcg_reg = 0x75010,
2767 .enable_reg = 0x75010,
2781 .halt_reg = 0x8c004,
2784 .enable_reg = 0x8c004,
2785 .enable_mask = BIT(0),
2794 .halt_reg = 0x7505c,
2796 .hwcg_reg = 0x7505c,
2799 .enable_reg = 0x7505c,
2800 .enable_mask = BIT(0),
2813 .halt_reg = 0x7505c,
2815 .hwcg_reg = 0x7505c,
2818 .enable_reg = 0x7505c,
2832 .halt_reg = 0x75090,
2834 .hwcg_reg = 0x75090,
2837 .enable_reg = 0x75090,
2838 .enable_mask = BIT(0),
2851 .halt_reg = 0x75090,
2853 .hwcg_reg = 0x75090,
2856 .enable_reg = 0x75090,
2873 .enable_reg = 0x7501c,
2874 .enable_mask = BIT(0),
2886 .enable_reg = 0x750ac,
2887 .enable_mask = BIT(0),
2899 .enable_reg = 0x75018,
2900 .enable_mask = BIT(0),
2909 .halt_reg = 0x75058,
2911 .hwcg_reg = 0x75058,
2914 .enable_reg = 0x75058,
2915 .enable_mask = BIT(0),
2928 .halt_reg = 0x75058,
2930 .hwcg_reg = 0x75058,
2933 .enable_reg = 0x75058,
2947 .halt_reg = 0x8c000,
2950 .enable_reg = 0x8c000,
2951 .enable_mask = BIT(0),
2960 .halt_reg = 0x77014,
2962 .hwcg_reg = 0x77014,
2965 .enable_reg = 0x77014,
2966 .enable_mask = BIT(0),
2975 .halt_reg = 0x77010,
2977 .hwcg_reg = 0x77010,
2980 .enable_reg = 0x77010,
2981 .enable_mask = BIT(0),
2994 .halt_reg = 0x77010,
2996 .hwcg_reg = 0x77010,
2999 .enable_reg = 0x77010,
3013 .halt_reg = 0x7705c,
3015 .hwcg_reg = 0x7705c,
3018 .enable_reg = 0x7705c,
3019 .enable_mask = BIT(0),
3032 .halt_reg = 0x7705c,
3034 .hwcg_reg = 0x7705c,
3037 .enable_reg = 0x7705c,
3051 .halt_reg = 0x77090,
3053 .hwcg_reg = 0x77090,
3056 .enable_reg = 0x77090,
3057 .enable_mask = BIT(0),
3070 .halt_reg = 0x77090,
3072 .hwcg_reg = 0x77090,
3075 .enable_reg = 0x77090,
3092 .enable_reg = 0x7701c,
3093 .enable_mask = BIT(0),
3105 .enable_reg = 0x770ac,
3106 .enable_mask = BIT(0),
3118 .enable_reg = 0x77018,
3119 .enable_mask = BIT(0),
3128 .halt_reg = 0x77058,
3130 .hwcg_reg = 0x77058,
3133 .enable_reg = 0x77058,
3134 .enable_mask = BIT(0),
3147 .halt_reg = 0x77058,
3149 .hwcg_reg = 0x77058,
3152 .enable_reg = 0x77058,
3166 .halt_reg = 0xf010,
3169 .enable_reg = 0xf010,
3170 .enable_mask = BIT(0),
3183 .halt_reg = 0xf018,
3186 .enable_reg = 0xf018,
3187 .enable_mask = BIT(0),
3200 .halt_reg = 0xf014,
3203 .enable_reg = 0xf014,
3204 .enable_mask = BIT(0),
3213 .halt_reg = 0x10010,
3216 .enable_reg = 0x10010,
3217 .enable_mask = BIT(0),
3230 .halt_reg = 0x10018,
3233 .enable_reg = 0x10018,
3234 .enable_mask = BIT(0),
3247 .halt_reg = 0x10014,
3250 .enable_reg = 0x10014,
3251 .enable_mask = BIT(0),
3260 .halt_reg = 0x8c008,
3263 .enable_reg = 0x8c008,
3264 .enable_mask = BIT(0),
3273 .halt_reg = 0xf050,
3276 .enable_reg = 0xf050,
3277 .enable_mask = BIT(0),
3290 .halt_reg = 0xf054,
3293 .enable_reg = 0xf054,
3294 .enable_mask = BIT(0),
3309 .enable_reg = 0xf058,
3310 .enable_mask = BIT(0),
3319 .halt_reg = 0x8c028,
3322 .enable_reg = 0x8c028,
3323 .enable_mask = BIT(0),
3332 .halt_reg = 0x10050,
3335 .enable_reg = 0x10050,
3336 .enable_mask = BIT(0),
3349 .halt_reg = 0x10054,
3352 .enable_reg = 0x10054,
3353 .enable_mask = BIT(0),
3368 .enable_reg = 0x10058,
3369 .enable_mask = BIT(0),
3382 .halt_reg = 0xb004,
3384 .hwcg_reg = 0xb004,
3387 .enable_reg = 0xb004,
3388 .enable_mask = BIT(0),
3398 .halt_reg = 0xb024,
3401 .enable_reg = 0xb024,
3402 .enable_mask = BIT(0),
3411 .halt_reg = 0xb028,
3414 .enable_reg = 0xb028,
3415 .enable_mask = BIT(0),
3424 .halt_reg = 0xb02c,
3427 .enable_reg = 0xb02c,
3428 .enable_mask = BIT(0),
3438 .halt_reg = 0xb040,
3441 .enable_reg = 0xb040,
3442 .enable_mask = BIT(0),
3452 .gdscr = 0xf004,
3461 .gdscr = 0x10004,
3685 [GCC_EMAC_BCR] = { 0x6000 },
3686 [GCC_GPU_BCR] = { 0x71000 },
3687 [GCC_MMSS_BCR] = { 0xb000 },
3688 [GCC_NPU_BCR] = { 0x4d000 },
3689 [GCC_PCIE_0_BCR] = { 0x6b000 },
3690 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3691 [GCC_PCIE_1_BCR] = { 0x8d000 },
3692 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3693 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3694 [GCC_PDM_BCR] = { 0x33000 },
3695 [GCC_PRNG_BCR] = { 0x34000 },
3696 [GCC_QSPI_BCR] = { 0x24008 },
3697 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3698 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3699 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3700 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3701 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3702 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3703 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3704 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3705 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3706 [GCC_SDCC2_BCR] = { 0x14000 },
3707 [GCC_SDCC4_BCR] = { 0x16000 },
3708 [GCC_TSIF_BCR] = { 0x36000 },
3709 [GCC_UFS_CARD_BCR] = { 0x75000 },
3710 [GCC_UFS_PHY_BCR] = { 0x77000 },
3711 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3712 [GCC_USB30_SEC_BCR] = { 0x10000 },
3713 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3725 .max_register = 0x9c040,
3754 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sm8150_probe()
3755 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sm8150_probe()