Lines Matching +full:0 +full:x6a000
39 { P_BI_TCXO, 0 },
53 { P_BI_TCXO, 0 },
69 { P_BI_TCXO, 0 },
81 { P_BI_TCXO, 0 },
93 { P_BI_TCXO, 0 },
103 { P_BI_TCXO, 0 },
138 { P_BI_TCXO, 0 },
154 .offset = 0x0,
157 .enable_reg = 0x52000,
158 .enable_mask = BIT(0),
169 .offset = 0x76000,
172 .enable_reg = 0x52000,
184 { 0x0, 1 },
185 { 0x1, 2 },
186 { 0x3, 4 },
187 { 0x7, 8 },
192 .offset = 0x0,
207 F(19200000, P_BI_TCXO, 1, 0, 0),
212 .cmd_rcgr = 0x48014,
213 .mnd_width = 0,
226 F(19200000, P_BI_TCXO, 1, 0, 0),
231 .cmd_rcgr = 0x4815c,
232 .mnd_width = 0,
245 F(19200000, P_BI_TCXO, 1, 0, 0),
246 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
247 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
248 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
249 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
254 .cmd_rcgr = 0x64004,
268 .cmd_rcgr = 0x65004,
282 .cmd_rcgr = 0x66004,
296 F(9600000, P_BI_TCXO, 2, 0, 0),
297 F(19200000, P_BI_TCXO, 1, 0, 0),
302 .cmd_rcgr = 0x6b028,
316 .cmd_rcgr = 0x8d028,
330 F(19200000, P_BI_TCXO, 1, 0, 0),
331 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
336 .cmd_rcgr = 0x6f014,
337 .mnd_width = 0,
350 F(19200000, P_BI_TCXO, 1, 0, 0),
351 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
352 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
353 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
358 .cmd_rcgr = 0x4b008,
359 .mnd_width = 0,
372 F(9600000, P_BI_TCXO, 2, 0, 0),
373 F(19200000, P_BI_TCXO, 1, 0, 0),
374 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
379 .cmd_rcgr = 0x33010,
380 .mnd_width = 0,
395 F(19200000, P_BI_TCXO, 1, 0, 0),
402 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
406 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
419 .cmd_rcgr = 0x17034,
435 .cmd_rcgr = 0x17164,
451 .cmd_rcgr = 0x17294,
467 .cmd_rcgr = 0x173c4,
483 .cmd_rcgr = 0x174f4,
499 .cmd_rcgr = 0x17624,
515 .cmd_rcgr = 0x17754,
531 .cmd_rcgr = 0x17884,
547 .cmd_rcgr = 0x18018,
563 .cmd_rcgr = 0x18148,
579 .cmd_rcgr = 0x18278,
595 .cmd_rcgr = 0x183a8,
611 .cmd_rcgr = 0x184d8,
627 .cmd_rcgr = 0x18608,
643 .cmd_rcgr = 0x18738,
659 .cmd_rcgr = 0x18868,
669 F(9600000, P_BI_TCXO, 2, 0, 0),
670 F(19200000, P_BI_TCXO, 1, 0, 0),
671 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
672 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
673 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
674 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
679 .cmd_rcgr = 0x1400c,
694 F(9600000, P_BI_TCXO, 2, 0, 0),
695 F(19200000, P_BI_TCXO, 1, 0, 0),
697 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
698 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
703 .cmd_rcgr = 0x1600c,
722 .cmd_rcgr = 0x36010,
736 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
737 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
738 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
739 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
740 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
745 .cmd_rcgr = 0x7501c,
759 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
760 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
761 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
762 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
767 .cmd_rcgr = 0x7505c,
768 .mnd_width = 0,
781 .cmd_rcgr = 0x75090,
782 .mnd_width = 0,
795 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
796 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
797 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
802 .cmd_rcgr = 0x75074,
803 .mnd_width = 0,
816 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
817 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
818 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
819 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
820 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
825 .cmd_rcgr = 0x7701c,
839 .cmd_rcgr = 0x7705c,
840 .mnd_width = 0,
853 .cmd_rcgr = 0x77090,
854 .mnd_width = 0,
867 .cmd_rcgr = 0x77074,
868 .mnd_width = 0,
881 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
882 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
883 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
884 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
885 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
890 .cmd_rcgr = 0xf018,
904 F(19200000, P_BI_TCXO, 1, 0, 0),
905 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
906 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
907 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
912 .cmd_rcgr = 0xf030,
913 .mnd_width = 0,
926 .cmd_rcgr = 0x10018,
940 .cmd_rcgr = 0x10030,
941 .mnd_width = 0,
954 .cmd_rcgr = 0xf05c,
955 .mnd_width = 0,
968 .cmd_rcgr = 0x1005c,
969 .mnd_width = 0,
982 .cmd_rcgr = 0x7a030,
983 .mnd_width = 0,
996 F(19200000, P_BI_TCXO, 1, 0, 0),
997 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
998 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
1003 .cmd_rcgr = 0x7a018,
1004 .mnd_width = 0,
1017 .halt_reg = 0x90014,
1020 .enable_reg = 0x90014,
1021 .enable_mask = BIT(0),
1030 .halt_reg = 0x82028,
1032 .hwcg_reg = 0x82028,
1035 .enable_reg = 0x82028,
1036 .enable_mask = BIT(0),
1050 .halt_reg = 0x82024,
1052 .hwcg_reg = 0x82024,
1055 .enable_reg = 0x82024,
1056 .enable_mask = BIT(0),
1070 .halt_reg = 0x8201c,
1073 .enable_reg = 0x8201c,
1074 .enable_mask = BIT(0),
1088 .halt_reg = 0x82020,
1091 .enable_reg = 0x82020,
1092 .enable_mask = BIT(0),
1106 .halt_reg = 0x7a050,
1109 .enable_reg = 0x7a050,
1110 .enable_mask = BIT(0),
1124 .halt_reg = 0x38004,
1126 .hwcg_reg = 0x38004,
1129 .enable_reg = 0x52004,
1139 .halt_reg = 0xb008,
1141 .hwcg_reg = 0xb008,
1144 .enable_reg = 0xb008,
1145 .enable_mask = BIT(0),
1155 .halt_reg = 0xb020,
1158 .enable_reg = 0xb020,
1159 .enable_mask = BIT(0),
1168 .halt_reg = 0xb02c,
1171 .enable_reg = 0xb02c,
1172 .enable_mask = BIT(0),
1182 .halt_reg = 0x4100c,
1184 .hwcg_reg = 0x4100c,
1187 .enable_reg = 0x52004,
1197 .halt_reg = 0x41008,
1200 .enable_reg = 0x52004,
1210 .halt_reg = 0x41004,
1213 .enable_reg = 0x52004,
1223 .halt_reg = 0x502c,
1226 .enable_reg = 0x502c,
1227 .enable_mask = BIT(0),
1241 .halt_reg = 0x5030,
1244 .enable_reg = 0x5030,
1245 .enable_mask = BIT(0),
1259 .halt_reg = 0x48000,
1262 .enable_reg = 0x52004,
1277 .halt_reg = 0x48008,
1280 .enable_reg = 0x48008,
1281 .enable_mask = BIT(0),
1295 .halt_reg = 0x44038,
1298 .enable_reg = 0x44038,
1299 .enable_mask = BIT(0),
1308 .halt_reg = 0xb00c,
1310 .hwcg_reg = 0xb00c,
1313 .enable_reg = 0xb00c,
1314 .enable_mask = BIT(0),
1324 .halt_reg = 0xb024,
1327 .enable_reg = 0xb024,
1328 .enable_mask = BIT(0),
1339 .enable_reg = 0x52004,
1355 .enable_reg = 0x52004,
1369 .halt_reg = 0xb030,
1372 .enable_reg = 0xb030,
1373 .enable_mask = BIT(0),
1383 .halt_reg = 0x64000,
1386 .enable_reg = 0x64000,
1387 .enable_mask = BIT(0),
1401 .halt_reg = 0x65000,
1404 .enable_reg = 0x65000,
1405 .enable_mask = BIT(0),
1419 .halt_reg = 0x66000,
1422 .enable_reg = 0x66000,
1423 .enable_mask = BIT(0),
1437 .halt_reg = 0x71004,
1439 .hwcg_reg = 0x71004,
1442 .enable_reg = 0x71004,
1443 .enable_mask = BIT(0),
1455 .enable_reg = 0x52004,
1471 .enable_reg = 0x52004,
1485 .halt_reg = 0x8c010,
1488 .enable_reg = 0x8c010,
1489 .enable_mask = BIT(0),
1498 .halt_reg = 0x7100c,
1501 .enable_reg = 0x7100c,
1502 .enable_mask = BIT(0),
1511 .halt_reg = 0x71018,
1514 .enable_reg = 0x71018,
1515 .enable_mask = BIT(0),
1524 .halt_reg = 0x7a04c,
1527 .enable_reg = 0x7a04c,
1528 .enable_mask = BIT(0),
1542 .halt_reg = 0x8a008,
1545 .enable_reg = 0x8a008,
1546 .enable_mask = BIT(0),
1555 .halt_reg = 0x8a000,
1557 .hwcg_reg = 0x8a000,
1560 .enable_reg = 0x8a000,
1561 .enable_mask = BIT(0),
1572 .enable_reg = 0x52004,
1582 .halt_reg = 0x8a004,
1584 .hwcg_reg = 0x8a004,
1587 .enable_reg = 0x8a004,
1588 .enable_mask = BIT(0),
1597 .halt_reg = 0x8a154,
1600 .enable_reg = 0x8a154,
1601 .enable_mask = BIT(0),
1610 .halt_reg = 0x8a150,
1613 .enable_reg = 0x8a150,
1614 .enable_mask = BIT(0),
1623 .halt_reg = 0x7a048,
1626 .enable_reg = 0x7a048,
1627 .enable_mask = BIT(0),
1641 .halt_reg = 0x6b01c,
1644 .enable_reg = 0x5200c,
1659 .halt_reg = 0x6b018,
1661 .hwcg_reg = 0x6b018,
1664 .enable_reg = 0x5200c,
1674 .halt_reg = 0x8c00c,
1677 .enable_reg = 0x8c00c,
1678 .enable_mask = BIT(0),
1687 .halt_reg = 0x6b014,
1690 .enable_reg = 0x5200c,
1702 .enable_reg = 0x5200c,
1715 .halt_reg = 0x6b010,
1717 .hwcg_reg = 0x6b010,
1720 .enable_reg = 0x5200c,
1721 .enable_mask = BIT(0),
1730 .halt_reg = 0x6b00c,
1733 .enable_reg = 0x5200c,
1743 .halt_reg = 0x8d01c,
1746 .enable_reg = 0x52004,
1761 .halt_reg = 0x8d018,
1763 .hwcg_reg = 0x8d018,
1766 .enable_reg = 0x52004,
1776 .halt_reg = 0x8c02c,
1779 .enable_reg = 0x8c02c,
1780 .enable_mask = BIT(0),
1789 .halt_reg = 0x8d014,
1792 .enable_reg = 0x52004,
1804 .enable_reg = 0x52004,
1816 .halt_reg = 0x8d010,
1818 .hwcg_reg = 0x8d010,
1821 .enable_reg = 0x52004,
1831 .halt_reg = 0x8d00c,
1834 .enable_reg = 0x52004,
1844 .halt_reg = 0x6f004,
1847 .enable_reg = 0x6f004,
1848 .enable_mask = BIT(0),
1862 .halt_reg = 0x6f02c,
1865 .enable_reg = 0x6f02c,
1866 .enable_mask = BIT(0),
1880 .halt_reg = 0x3300c,
1883 .enable_reg = 0x3300c,
1884 .enable_mask = BIT(0),
1898 .halt_reg = 0x33004,
1900 .hwcg_reg = 0x33004,
1903 .enable_reg = 0x33004,
1904 .enable_mask = BIT(0),
1913 .halt_reg = 0x33008,
1916 .enable_reg = 0x33008,
1917 .enable_mask = BIT(0),
1926 .halt_reg = 0x34004,
1928 .hwcg_reg = 0x34004,
1931 .enable_reg = 0x52004,
1941 .halt_reg = 0xb014,
1943 .hwcg_reg = 0xb014,
1946 .enable_reg = 0xb014,
1947 .enable_mask = BIT(0),
1956 .halt_reg = 0xb018,
1958 .hwcg_reg = 0xb018,
1961 .enable_reg = 0xb018,
1962 .enable_mask = BIT(0),
1971 .halt_reg = 0xb010,
1973 .hwcg_reg = 0xb010,
1976 .enable_reg = 0xb010,
1977 .enable_mask = BIT(0),
1986 .halt_reg = 0x4b000,
1989 .enable_reg = 0x4b000,
1990 .enable_mask = BIT(0),
1999 .halt_reg = 0x4b004,
2002 .enable_reg = 0x4b004,
2003 .enable_mask = BIT(0),
2017 .halt_reg = 0x17030,
2020 .enable_reg = 0x5200c,
2035 .halt_reg = 0x17160,
2038 .enable_reg = 0x5200c,
2053 .halt_reg = 0x17290,
2056 .enable_reg = 0x5200c,
2071 .halt_reg = 0x173c0,
2074 .enable_reg = 0x5200c,
2089 .halt_reg = 0x174f0,
2092 .enable_reg = 0x5200c,
2107 .halt_reg = 0x17620,
2110 .enable_reg = 0x5200c,
2125 .halt_reg = 0x17750,
2128 .enable_reg = 0x5200c,
2143 .halt_reg = 0x17880,
2146 .enable_reg = 0x5200c,
2161 .halt_reg = 0x18014,
2164 .enable_reg = 0x5200c,
2179 .halt_reg = 0x18144,
2182 .enable_reg = 0x5200c,
2197 .halt_reg = 0x18274,
2200 .enable_reg = 0x5200c,
2215 .halt_reg = 0x183a4,
2218 .enable_reg = 0x5200c,
2233 .halt_reg = 0x184d4,
2236 .enable_reg = 0x5200c,
2251 .halt_reg = 0x18604,
2254 .enable_reg = 0x5200c,
2269 .halt_reg = 0x18734,
2272 .enable_reg = 0x5200c,
2287 .halt_reg = 0x18864,
2290 .enable_reg = 0x5200c,
2305 .halt_reg = 0x17004,
2308 .enable_reg = 0x5200c,
2318 .halt_reg = 0x17008,
2320 .hwcg_reg = 0x17008,
2323 .enable_reg = 0x5200c,
2333 .halt_reg = 0x1800c,
2336 .enable_reg = 0x5200c,
2346 .halt_reg = 0x18010,
2348 .hwcg_reg = 0x18010,
2351 .enable_reg = 0x5200c,
2361 .halt_reg = 0x14008,
2364 .enable_reg = 0x14008,
2365 .enable_mask = BIT(0),
2374 .halt_reg = 0x14004,
2377 .enable_reg = 0x14004,
2378 .enable_mask = BIT(0),
2392 .halt_reg = 0x16008,
2395 .enable_reg = 0x16008,
2396 .enable_mask = BIT(0),
2405 .halt_reg = 0x16004,
2408 .enable_reg = 0x16004,
2409 .enable_mask = BIT(0),
2423 .halt_reg = 0x414c,
2426 .enable_reg = 0x52004,
2427 .enable_mask = BIT(0),
2441 .halt_reg = 0x36004,
2444 .enable_reg = 0x36004,
2445 .enable_mask = BIT(0),
2454 .halt_reg = 0x3600c,
2457 .enable_reg = 0x3600c,
2458 .enable_mask = BIT(0),
2467 .halt_reg = 0x36008,
2470 .enable_reg = 0x36008,
2471 .enable_mask = BIT(0),
2485 .halt_reg = 0x75010,
2487 .hwcg_reg = 0x75010,
2490 .enable_reg = 0x75010,
2491 .enable_mask = BIT(0),
2500 .halt_reg = 0x7500c,
2502 .hwcg_reg = 0x7500c,
2505 .enable_reg = 0x7500c,
2506 .enable_mask = BIT(0),
2520 .halt_reg = 0x8c004,
2523 .enable_reg = 0x8c004,
2524 .enable_mask = BIT(0),
2533 .halt_reg = 0x75058,
2535 .hwcg_reg = 0x75058,
2538 .enable_reg = 0x75058,
2539 .enable_mask = BIT(0),
2553 .halt_reg = 0x7508c,
2555 .hwcg_reg = 0x7508c,
2558 .enable_reg = 0x7508c,
2559 .enable_mask = BIT(0),
2575 .enable_reg = 0x75018,
2576 .enable_mask = BIT(0),
2587 .enable_reg = 0x750a8,
2588 .enable_mask = BIT(0),
2599 .enable_reg = 0x75014,
2600 .enable_mask = BIT(0),
2609 .halt_reg = 0x75054,
2611 .hwcg_reg = 0x75054,
2614 .enable_reg = 0x75054,
2615 .enable_mask = BIT(0),
2629 .halt_reg = 0x8c000,
2632 .enable_reg = 0x8c000,
2633 .enable_mask = BIT(0),
2642 .halt_reg = 0x77010,
2644 .hwcg_reg = 0x77010,
2647 .enable_reg = 0x77010,
2648 .enable_mask = BIT(0),
2657 .halt_reg = 0x7700c,
2659 .hwcg_reg = 0x7700c,
2662 .enable_reg = 0x7700c,
2663 .enable_mask = BIT(0),
2677 .halt_reg = 0x77058,
2679 .hwcg_reg = 0x77058,
2682 .enable_reg = 0x77058,
2683 .enable_mask = BIT(0),
2697 .halt_reg = 0x7708c,
2699 .hwcg_reg = 0x7708c,
2702 .enable_reg = 0x7708c,
2703 .enable_mask = BIT(0),
2719 .enable_reg = 0x77018,
2720 .enable_mask = BIT(0),
2731 .enable_reg = 0x770a8,
2732 .enable_mask = BIT(0),
2743 .enable_reg = 0x77014,
2744 .enable_mask = BIT(0),
2753 .halt_reg = 0x77054,
2755 .hwcg_reg = 0x77054,
2758 .enable_reg = 0x77054,
2759 .enable_mask = BIT(0),
2773 .halt_reg = 0xf00c,
2776 .enable_reg = 0xf00c,
2777 .enable_mask = BIT(0),
2791 .halt_reg = 0xf014,
2794 .enable_reg = 0xf014,
2795 .enable_mask = BIT(0),
2809 .halt_reg = 0xf010,
2812 .enable_reg = 0xf010,
2813 .enable_mask = BIT(0),
2822 .halt_reg = 0x1000c,
2825 .enable_reg = 0x1000c,
2826 .enable_mask = BIT(0),
2840 .halt_reg = 0x10014,
2843 .enable_reg = 0x10014,
2844 .enable_mask = BIT(0),
2858 .halt_reg = 0x10010,
2861 .enable_reg = 0x10010,
2862 .enable_mask = BIT(0),
2871 .halt_reg = 0x8c008,
2874 .enable_reg = 0x8c008,
2875 .enable_mask = BIT(0),
2884 .halt_reg = 0xf04c,
2887 .enable_reg = 0xf04c,
2888 .enable_mask = BIT(0),
2902 .halt_reg = 0xf050,
2905 .enable_reg = 0xf050,
2906 .enable_mask = BIT(0),
2922 .enable_reg = 0xf054,
2923 .enable_mask = BIT(0),
2932 .halt_reg = 0x8c028,
2935 .enable_reg = 0x8c028,
2936 .enable_mask = BIT(0),
2945 .halt_reg = 0x1004c,
2948 .enable_reg = 0x1004c,
2949 .enable_mask = BIT(0),
2963 .halt_reg = 0x10050,
2966 .enable_reg = 0x10050,
2967 .enable_mask = BIT(0),
2983 .enable_reg = 0x10054,
2984 .enable_mask = BIT(0),
2993 .halt_reg = 0x6a004,
2995 .hwcg_reg = 0x6a004,
2998 .enable_reg = 0x6a004,
2999 .enable_mask = BIT(0),
3008 .halt_reg = 0x7a00c,
3011 .enable_reg = 0x7a00c,
3012 .enable_mask = BIT(0),
3026 .halt_reg = 0x7a004,
3029 .enable_reg = 0x7a004,
3030 .enable_mask = BIT(0),
3044 .halt_reg = 0x7a008,
3047 .enable_reg = 0x7a008,
3048 .enable_mask = BIT(0),
3062 .halt_reg = 0xb004,
3064 .hwcg_reg = 0xb004,
3067 .enable_reg = 0xb004,
3068 .enable_mask = BIT(0),
3078 .halt_reg = 0xb01c,
3081 .enable_reg = 0xb01c,
3082 .enable_mask = BIT(0),
3091 .halt_reg = 0xb028,
3094 .enable_reg = 0xb028,
3095 .enable_mask = BIT(0),
3105 .halt_reg = 0x7a014,
3107 .hwcg_reg = 0x7a014,
3110 .enable_reg = 0x7a014,
3111 .enable_mask = BIT(0),
3120 .halt_reg = 0x7a010,
3123 .enable_reg = 0x7a010,
3124 .enable_mask = BIT(0),
3138 .halt_reg = 0x48190,
3141 .enable_reg = 0x48190,
3142 .enable_mask = BIT(0),
3152 .halt_reg = 0x48004,
3154 .hwcg_reg = 0x48004,
3157 .enable_reg = 0x52004,
3170 .halt_reg = 0x47000,
3173 .enable_reg = 0x47000,
3174 .enable_mask = BIT(0),
3184 .halt_reg = 0x47008,
3187 .enable_reg = 0x47008,
3188 .enable_mask = BIT(0),
3199 .gdscr = 0x6b004,
3208 .gdscr = 0x8d004,
3217 .gdscr = 0x75004,
3226 .gdscr = 0x77004,
3235 .gdscr = 0xf004,
3244 .gdscr = 0x10004,
3253 .gdscr = 0x7d030,
3262 .gdscr = 0x7d03c,
3271 .gdscr = 0x7d034,
3280 .gdscr = 0x7d038,
3289 .gdscr = 0x7d040,
3298 .gdscr = 0x7d048,
3307 .gdscr = 0x7d044,
3512 [GCC_MMSS_BCR] = { 0xb000 },
3513 [GCC_PCIE_0_BCR] = { 0x6b000 },
3514 [GCC_PCIE_1_BCR] = { 0x8d000 },
3515 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3516 [GCC_PDM_BCR] = { 0x33000 },
3517 [GCC_PRNG_BCR] = { 0x34000 },
3518 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3519 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3520 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3521 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3522 [GCC_SDCC2_BCR] = { 0x14000 },
3523 [GCC_SDCC4_BCR] = { 0x16000 },
3524 [GCC_TSIF_BCR] = { 0x36000 },
3525 [GCC_UFS_CARD_BCR] = { 0x75000 },
3526 [GCC_UFS_PHY_BCR] = { 0x77000 },
3527 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3528 [GCC_USB30_SEC_BCR] = { 0x10000 },
3529 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3530 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3531 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3532 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3533 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3534 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3535 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3536 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3537 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3566 .max_register = 0x182090,
3615 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); in gcc_sdm845_probe()
3616 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sdm845_probe()