Lines Matching +full:0 +full:x6a000
41 { P_XO, 0 },
53 { P_XO, 0 },
63 { P_XO, 0 },
77 { P_XO, 0 },
87 { P_XO, 0 },
97 { P_XO, 0 },
115 { P_XO, 0 },
129 { P_XO, 0 },
154 .offset = 0x0,
157 .enable_reg = 0x52000,
158 .enable_mask = BIT(0),
180 .offset = 0x00000,
191 .offset = 0x1000,
194 .enable_reg = 0x52000,
217 .offset = 0x1000,
228 .offset = 0x77000,
231 .enable_reg = 0x52000,
243 .offset = 0x77000,
255 F(19200000, P_XO, 1, 0, 0),
256 F(50000000, P_GPLL0, 12, 0, 0),
261 .cmd_rcgr = 0x19020,
262 .mnd_width = 0,
276 F(4800000, P_XO, 4, 0, 0),
277 F(9600000, P_XO, 2, 0, 0),
279 F(19200000, P_XO, 1, 0, 0),
281 F(50000000, P_GPLL0, 12, 0, 0),
286 .cmd_rcgr = 0x1900c,
300 .cmd_rcgr = 0x1b020,
301 .mnd_width = 0,
314 .cmd_rcgr = 0x1b00c,
328 .cmd_rcgr = 0x1d020,
329 .mnd_width = 0,
342 .cmd_rcgr = 0x1d00c,
356 .cmd_rcgr = 0x1f020,
357 .mnd_width = 0,
370 .cmd_rcgr = 0x1f00c,
388 F(19200000, P_XO, 1, 0, 0),
391 F(40000000, P_GPLL0, 15, 0, 0),
393 F(48000000, P_GPLL0, 12.5, 0, 0),
397 F(60000000, P_GPLL0, 10, 0, 0),
398 F(63157895, P_GPLL0, 9.5, 0, 0),
403 .cmd_rcgr = 0x1a00c,
417 .cmd_rcgr = 0x1c00c,
431 .cmd_rcgr = 0x26020,
432 .mnd_width = 0,
445 .cmd_rcgr = 0x2600c,
459 .cmd_rcgr = 0x28020,
460 .mnd_width = 0,
473 .cmd_rcgr = 0x2800c,
487 .cmd_rcgr = 0x2a020,
488 .mnd_width = 0,
501 .cmd_rcgr = 0x2a00c,
515 .cmd_rcgr = 0x2c020,
516 .mnd_width = 0,
529 .cmd_rcgr = 0x2c00c,
543 .cmd_rcgr = 0x2700c,
557 .cmd_rcgr = 0x2900c,
571 F(19200000, P_XO, 1, 0, 0),
572 F(100000000, P_GPLL0, 6, 0, 0),
573 F(200000000, P_GPLL0, 3, 0, 0),
578 .cmd_rcgr = 0x64004,
592 .cmd_rcgr = 0x65004,
606 .cmd_rcgr = 0x66004,
620 F(300000000, P_GPLL0, 2, 0, 0),
621 F(600000000, P_GPLL0, 1, 0, 0),
626 .cmd_rcgr = 0x4805c,
627 .mnd_width = 0,
640 F(384000000, P_GPLL4, 4, 0, 0),
641 F(768000000, P_GPLL4, 2, 0, 0),
642 F(1536000000, P_GPLL4, 1, 0, 0),
647 .cmd_rcgr = 0x48074,
648 .mnd_width = 0,
661 F(19200000, P_XO, 1, 0, 0),
666 .cmd_rcgr = 0x48044,
667 .mnd_width = 0,
680 F(60000000, P_GPLL0, 10, 0, 0),
685 .cmd_rcgr = 0x33010,
686 .mnd_width = 0,
699 F(19200000, P_XO, 1, 0, 0),
700 F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
701 F(160400000, P_GPLL1, 5, 0, 0),
702 F(267333333, P_GPLL1, 3, 0, 0),
707 .cmd_rcgr = 0x4d00c,
708 .mnd_width = 0,
725 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
726 F(100000000, P_GPLL0, 6, 0, 0),
727 F(192000000, P_GPLL4, 8, 0, 0),
728 F(384000000, P_GPLL4, 4, 0, 0),
733 .cmd_rcgr = 0x1602c,
747 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
748 F(150000000, P_GPLL0, 4, 0, 0),
749 F(200000000, P_GPLL0, 3, 0, 0),
750 F(300000000, P_GPLL0, 2, 0, 0),
755 .cmd_rcgr = 0x16010,
756 .mnd_width = 0,
773 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
774 F(100000000, P_GPLL0, 6, 0, 0),
775 F(192000000, P_GPLL4, 8, 0, 0),
776 F(200000000, P_GPLL0, 3, 0, 0),
781 .cmd_rcgr = 0x14010,
795 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
796 F(100000000, P_GPLL0, 6, 0, 0),
797 F(150000000, P_GPLL0, 4, 0, 0),
798 F(200000000, P_GPLL0, 3, 0, 0),
799 F(240000000, P_GPLL0, 2.5, 0, 0),
804 .cmd_rcgr = 0x75018,
818 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
819 F(150000000, P_GPLL0, 4, 0, 0),
820 F(300000000, P_GPLL0, 2, 0, 0),
825 .cmd_rcgr = 0x76010,
826 .mnd_width = 0,
839 .cmd_rcgr = 0x76044,
840 .mnd_width = 0,
853 F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
854 F(75000000, P_GPLL0, 8, 0, 0),
855 F(150000000, P_GPLL0, 4, 0, 0),
860 .cmd_rcgr = 0x76028,
861 .mnd_width = 0,
874 F(19200000, P_XO, 1, 0, 0),
875 F(60000000, P_GPLL0, 10, 0, 0),
876 F(120000000, P_GPLL0, 5, 0, 0),
881 .cmd_rcgr = 0x2f010,
895 F(19200000, P_XO, 1, 0, 0),
896 F(60000000, P_GPLL0, 10, 0, 0),
901 .cmd_rcgr = 0x2f024,
902 .mnd_width = 0,
915 F(19200000, P_XO, 1, 0, 0),
916 F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
917 F(120000000, P_GPLL0, 5, 0, 0),
918 F(133333333, P_GPLL0, 4.5, 0, 0),
919 F(150000000, P_GPLL0, 4, 0, 0),
920 F(200000000, P_GPLL0, 3, 0, 0),
921 F(240000000, P_GPLL0, 2.5, 0, 0),
926 .cmd_rcgr = 0xf014,
940 F(19200000, P_XO, 1, 0, 0),
941 F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
942 F(60000000, P_GPLL0, 10, 0, 0),
947 .cmd_rcgr = 0xf028,
948 .mnd_width = 0,
961 F(1200000, P_XO, 16, 0, 0),
962 F(19200000, P_XO, 1, 0, 0),
967 .cmd_rcgr = 0x5000c,
968 .mnd_width = 0,
981 .halt_reg = 0x75034,
984 .enable_reg = 0x75034,
985 .enable_mask = BIT(0),
998 .halt_reg = 0xf03c,
1001 .enable_reg = 0xf03c,
1002 .enable_mask = BIT(0),
1015 .halt_reg = 0x7106c,
1018 .enable_reg = 0x7106c,
1019 .enable_mask = BIT(0),
1028 .halt_reg = 0x48004,
1031 .enable_reg = 0x52004,
1041 .halt_reg = 0x4401c,
1044 .enable_reg = 0x4401c,
1045 .enable_mask = BIT(0),
1054 .halt_reg = 0x17004,
1057 .enable_reg = 0x52004,
1067 .halt_reg = 0x19008,
1070 .enable_reg = 0x19008,
1071 .enable_mask = BIT(0),
1085 .halt_reg = 0x19004,
1088 .enable_reg = 0x19004,
1089 .enable_mask = BIT(0),
1103 .halt_reg = 0x1b008,
1106 .enable_reg = 0x1b008,
1107 .enable_mask = BIT(0),
1121 .halt_reg = 0x1b004,
1124 .enable_reg = 0x1b004,
1125 .enable_mask = BIT(0),
1139 .halt_reg = 0x1d008,
1142 .enable_reg = 0x1d008,
1143 .enable_mask = BIT(0),
1157 .halt_reg = 0x1d004,
1160 .enable_reg = 0x1d004,
1161 .enable_mask = BIT(0),
1175 .halt_reg = 0x1f008,
1178 .enable_reg = 0x1f008,
1179 .enable_mask = BIT(0),
1193 .halt_reg = 0x1f004,
1196 .enable_reg = 0x1f004,
1197 .enable_mask = BIT(0),
1211 .halt_reg = 0x1a004,
1214 .enable_reg = 0x1a004,
1215 .enable_mask = BIT(0),
1229 .halt_reg = 0x1c004,
1232 .enable_reg = 0x1c004,
1233 .enable_mask = BIT(0),
1247 .halt_reg = 0x25004,
1250 .enable_reg = 0x52004,
1260 .halt_reg = 0x26008,
1263 .enable_reg = 0x26008,
1264 .enable_mask = BIT(0),
1278 .halt_reg = 0x26004,
1281 .enable_reg = 0x26004,
1282 .enable_mask = BIT(0),
1296 .halt_reg = 0x28008,
1299 .enable_reg = 0x28008,
1300 .enable_mask = BIT(0),
1314 .halt_reg = 0x28004,
1317 .enable_reg = 0x28004,
1318 .enable_mask = BIT(0),
1332 .halt_reg = 0x2a008,
1335 .enable_reg = 0x2a008,
1336 .enable_mask = BIT(0),
1350 .halt_reg = 0x2a004,
1353 .enable_reg = 0x2a004,
1354 .enable_mask = BIT(0),
1368 .halt_reg = 0x2c008,
1371 .enable_reg = 0x2c008,
1372 .enable_mask = BIT(0),
1386 .halt_reg = 0x2c004,
1389 .enable_reg = 0x2c004,
1390 .enable_mask = BIT(0),
1404 .halt_reg = 0x27004,
1407 .enable_reg = 0x27004,
1408 .enable_mask = BIT(0),
1422 .halt_reg = 0x29004,
1425 .enable_reg = 0x29004,
1426 .enable_mask = BIT(0),
1440 .halt_reg = 0x38004,
1443 .enable_reg = 0x52004,
1453 .halt_reg = 0x5058,
1456 .enable_reg = 0x5058,
1457 .enable_mask = BIT(0),
1470 .halt_reg = 0x5018,
1473 .enable_reg = 0x5018,
1474 .enable_mask = BIT(0),
1487 .halt_reg = 0x84004,
1489 .enable_reg = 0x84004,
1490 .enable_mask = BIT(0),
1499 .halt_reg = 0x64000,
1502 .enable_reg = 0x64000,
1503 .enable_mask = BIT(0),
1517 .halt_reg = 0x65000,
1520 .enable_reg = 0x65000,
1521 .enable_mask = BIT(0),
1535 .halt_reg = 0x66000,
1538 .enable_reg = 0x66000,
1539 .enable_mask = BIT(0),
1553 .halt_reg = 0x71010,
1556 .enable_reg = 0x71010,
1557 .enable_mask = BIT(0),
1566 .halt_reg = 0x71004,
1569 .enable_reg = 0x71004,
1570 .enable_mask = BIT(0),
1579 .halt_reg = 0x5200c,
1582 .enable_reg = 0x5200c,
1596 .halt_reg = 0x5200c,
1599 .enable_reg = 0x5200c,
1613 .halt_reg = 0x4808c,
1616 .enable_reg = 0x4808c,
1617 .enable_mask = BIT(0),
1627 .halt_reg = 0x48008,
1630 .enable_reg = 0x48008,
1631 .enable_mask = BIT(0),
1645 .halt_reg = 0x5200c,
1648 .enable_reg = 0x5200c,
1662 .halt_reg = 0x5200c,
1665 .enable_reg = 0x5200c,
1666 .enable_mask = BIT(0),
1679 .halt_reg = 0x9004,
1682 .enable_reg = 0x9004,
1683 .enable_mask = BIT(0),
1692 .halt_reg = 0x9000,
1695 .enable_reg = 0x9000,
1696 .enable_mask = BIT(0),
1705 .halt_reg = 0x8a000,
1707 .enable_reg = 0x8a000,
1708 .enable_mask = BIT(0),
1717 .halt_reg = 0x8a004,
1719 .hwcg_reg = 0x8a004,
1722 .enable_reg = 0x8a004,
1723 .enable_mask = BIT(0),
1732 .halt_reg = 0x8a040,
1734 .enable_reg = 0x8a040,
1735 .enable_mask = BIT(0),
1744 .halt_reg = 0x8a03c,
1746 .enable_reg = 0x8a03c,
1747 .enable_mask = BIT(0),
1756 .halt_reg = 0x3300c,
1759 .enable_reg = 0x3300c,
1760 .enable_mask = BIT(0),
1774 .halt_reg = 0x33004,
1777 .enable_reg = 0x33004,
1778 .enable_mask = BIT(0),
1787 .halt_reg = 0x34004,
1790 .enable_reg = 0x52004,
1800 .halt_reg = 0x4d004,
1803 .enable_reg = 0x4d004,
1804 .enable_mask = BIT(0),
1813 .halt_reg = 0x4d008,
1816 .enable_reg = 0x4d008,
1817 .enable_mask = BIT(0),
1831 .halt_reg = 0x88018,
1834 .enable_reg = 0x88018,
1835 .enable_mask = BIT(0),
1844 .halt_reg = 0x88014,
1847 .enable_reg = 0x88014,
1848 .enable_mask = BIT(0),
1857 .halt_reg = 0x16008,
1860 .enable_reg = 0x16008,
1861 .enable_mask = BIT(0),
1870 .halt_reg = 0x16004,
1873 .enable_reg = 0x16004,
1874 .enable_mask = BIT(0),
1888 .halt_reg = 0x1600c,
1891 .enable_reg = 0x1600c,
1892 .enable_mask = BIT(0),
1906 .halt_reg = 0x14008,
1909 .enable_reg = 0x14008,
1910 .enable_mask = BIT(0),
1919 .halt_reg = 0x14004,
1922 .enable_reg = 0x14004,
1923 .enable_mask = BIT(0),
1937 .halt_reg = 0x7500c,
1940 .enable_reg = 0x7500c,
1941 .enable_mask = BIT(0),
1950 .halt_reg = 0x75008,
1953 .enable_reg = 0x75008,
1954 .enable_mask = BIT(0),
1968 .halt_reg = 0x88008,
1971 .enable_reg = 0x88008,
1972 .enable_mask = BIT(0),
1981 .halt_reg = 0x7600c,
1984 .enable_reg = 0x7600c,
1985 .enable_mask = BIT(0),
1999 .halt_reg = 0x76040,
2002 .enable_reg = 0x76040,
2003 .enable_mask = BIT(0),
2017 .halt_reg = 0x75014,
2020 .enable_reg = 0x75014,
2021 .enable_mask = BIT(0),
2030 .halt_reg = 0x7605c,
2033 .enable_reg = 0x7605c,
2034 .enable_mask = BIT(0),
2043 .halt_reg = 0x75010,
2046 .enable_reg = 0x75010,
2047 .enable_mask = BIT(0),
2056 .halt_reg = 0x76008,
2059 .enable_reg = 0x76008,
2060 .enable_mask = BIT(0),
2074 .halt_reg = 0x2f004,
2077 .enable_reg = 0x2f004,
2078 .enable_mask = BIT(0),
2092 .halt_reg = 0x2f00c,
2095 .enable_reg = 0x2f00c,
2096 .enable_mask = BIT(0),
2110 .halt_reg = 0x2f008,
2113 .enable_reg = 0x2f008,
2114 .enable_mask = BIT(0),
2123 .halt_reg = 0xf008,
2126 .enable_reg = 0xf008,
2127 .enable_mask = BIT(0),
2141 .halt_reg = 0xf010,
2144 .enable_reg = 0xf010,
2145 .enable_mask = BIT(0),
2159 .halt_reg = 0xf00c,
2162 .enable_reg = 0xf00c,
2163 .enable_mask = BIT(0),
2172 .halt_reg = 0x8800c,
2175 .enable_reg = 0x8800c,
2176 .enable_mask = BIT(0),
2185 .halt_reg = 0x50000,
2188 .enable_reg = 0x50000,
2189 .enable_mask = BIT(0),
2203 .halt_reg = 0x50004,
2206 .enable_reg = 0x50004,
2207 .enable_mask = BIT(0),
2216 .halt_reg = 0x6a004,
2219 .enable_reg = 0x6a004,
2220 .enable_mask = BIT(0),
2229 .gdscr = 0x75004,
2230 .gds_hw_ctrl = 0x0,
2239 .gdscr = 0xf004,
2240 .gds_hw_ctrl = 0x0,
2249 .gdscr = 0x6b004,
2250 .gds_hw_ctrl = 0x0,
2399 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2400 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2401 [GCC_UFS_BCR] = { 0x75000 },
2402 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
2403 [GCC_USB3_PHY_BCR] = { 0x50020 },
2404 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
2405 [GCC_USB_20_BCR] = { 0x2f000 },
2406 [GCC_USB_30_BCR] = { 0xf000 },
2407 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2408 [GCC_MSS_RESTART] = { 0x79000 },
2415 .max_register = 0x94000,
2451 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); in gcc_sdm660_probe()