Lines Matching +full:0 +full:x6a000

37 	.offset = 0x0,
40 .enable_reg = 0x52010,
41 .enable_mask = BIT(0),
55 { 0x1, 2 },
60 .offset = 0x0,
90 .offset = 0x01000,
93 .enable_reg = 0x52010,
108 .offset = 0x76000,
111 .enable_reg = 0x52010,
126 .offset = 0x13000,
129 .enable_reg = 0x52010,
144 .offset = 0x27000,
147 .enable_reg = 0x52010,
162 { P_BI_TCXO, 0 },
183 { P_BI_TCXO, 0 },
199 { P_BI_TCXO, 0 },
217 { P_BI_TCXO, 0 },
229 { P_BI_TCXO, 0 },
245 { P_BI_TCXO, 0 },
261 { P_BI_TCXO, 0 },
275 F(19200000, P_BI_TCXO, 1, 0, 0),
280 .cmd_rcgr = 0x48014,
281 .mnd_width = 0,
295 F(19200000, P_BI_TCXO, 1, 0, 0),
296 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
297 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
298 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
299 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
304 .cmd_rcgr = 0x64004,
318 .cmd_rcgr = 0x65004,
332 .cmd_rcgr = 0x66004,
346 F(19200000, P_BI_TCXO, 1, 0, 0),
347 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
352 .cmd_rcgr = 0x33010,
353 .mnd_width = 0,
366 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
367 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
368 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
373 .cmd_rcgr = 0x4b00c,
374 .mnd_width = 0,
389 F(19200000, P_BI_TCXO, 1, 0, 0),
393 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
395 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
398 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
402 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
403 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
415 .cmd_rcgr = 0x17034,
431 .cmd_rcgr = 0x17164,
447 .cmd_rcgr = 0x17294,
463 .cmd_rcgr = 0x173c4,
479 .cmd_rcgr = 0x174f4,
495 .cmd_rcgr = 0x17624,
511 .cmd_rcgr = 0x18018,
527 .cmd_rcgr = 0x18148,
543 .cmd_rcgr = 0x18278,
559 .cmd_rcgr = 0x183a8,
575 .cmd_rcgr = 0x184d8,
591 .cmd_rcgr = 0x18608,
603 F(19200000, P_BI_TCXO, 1, 0, 0),
606 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
607 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
608 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
609 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
614 .cmd_rcgr = 0x12028,
628 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
629 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
630 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
631 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
636 .cmd_rcgr = 0x12010,
637 .mnd_width = 0,
651 F(9600000, P_BI_TCXO, 2, 0, 0),
652 F(19200000, P_BI_TCXO, 1, 0, 0),
653 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
654 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
655 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
660 .cmd_rcgr = 0x1400c,
674 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
675 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
676 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
677 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
678 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
683 .cmd_rcgr = 0x77020,
697 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
698 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
699 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
700 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
705 .cmd_rcgr = 0x77048,
706 .mnd_width = 0,
719 F(9600000, P_BI_TCXO, 2, 0, 0),
720 F(19200000, P_BI_TCXO, 1, 0, 0),
725 .cmd_rcgr = 0x77098,
726 .mnd_width = 0,
739 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
740 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
741 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
746 .cmd_rcgr = 0x77060,
747 .mnd_width = 0,
760 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
761 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
762 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
763 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
768 .cmd_rcgr = 0xf01c,
782 F(19200000, P_BI_TCXO, 1, 0, 0),
783 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
788 .cmd_rcgr = 0xf034,
789 .mnd_width = 0,
802 F(19200000, P_BI_TCXO, 1, 0, 0),
807 .cmd_rcgr = 0xf060,
808 .mnd_width = 0,
821 F(4800000, P_BI_TCXO, 4, 0, 0),
822 F(19200000, P_BI_TCXO, 1, 0, 0),
827 .cmd_rcgr = 0x3d030,
828 .mnd_width = 0,
841 .halt_reg = 0x82024,
843 .hwcg_reg = 0x82024,
846 .enable_reg = 0x82024,
847 .enable_mask = BIT(0),
861 .halt_reg = 0x8201c,
864 .enable_reg = 0x8201c,
865 .enable_mask = BIT(0),
879 .halt_reg = 0x38004,
881 .hwcg_reg = 0x38004,
884 .enable_reg = 0x52000,
894 .halt_reg = 0xb008,
896 .hwcg_reg = 0xb008,
899 .enable_reg = 0xb008,
900 .enable_mask = BIT(0),
909 .halt_reg = 0xb020,
912 .enable_reg = 0xb020,
913 .enable_mask = BIT(0),
922 .halt_reg = 0xb080,
924 .hwcg_reg = 0xb080,
927 .enable_reg = 0xb080,
928 .enable_mask = BIT(0),
937 .halt_reg = 0xb02c,
940 .enable_reg = 0xb02c,
941 .enable_mask = BIT(0),
950 .halt_reg = 0x4100c,
952 .hwcg_reg = 0x4100c,
955 .enable_reg = 0x52000,
965 .halt_reg = 0x41008,
968 .enable_reg = 0x52000,
978 .halt_reg = 0x41004,
981 .enable_reg = 0x52000,
991 .halt_reg = 0x502c,
994 .enable_reg = 0x502c,
995 .enable_mask = BIT(0),
1010 .halt_reg = 0x48000,
1013 .enable_reg = 0x52000,
1028 .halt_reg = 0x48008,
1031 .enable_reg = 0x48008,
1032 .enable_mask = BIT(0),
1041 .halt_reg = 0x4452c,
1044 .enable_reg = 0x4452c,
1045 .enable_mask = BIT(0),
1056 .enable_reg = 0x52000,
1072 .enable_reg = 0x52000,
1086 .halt_reg = 0xb024,
1089 .enable_reg = 0xb024,
1090 .enable_mask = BIT(0),
1099 .halt_reg = 0xb084,
1101 .hwcg_reg = 0xb084,
1104 .enable_reg = 0xb084,
1105 .enable_mask = BIT(0),
1114 .halt_reg = 0xb030,
1117 .enable_reg = 0xb030,
1118 .enable_mask = BIT(0),
1127 .halt_reg = 0x64000,
1130 .enable_reg = 0x64000,
1131 .enable_mask = BIT(0),
1145 .halt_reg = 0x65000,
1148 .enable_reg = 0x65000,
1149 .enable_mask = BIT(0),
1163 .halt_reg = 0x66000,
1166 .enable_reg = 0x66000,
1167 .enable_mask = BIT(0),
1183 .enable_reg = 0x52000,
1199 .enable_reg = 0x52000,
1213 .halt_reg = 0x7100c,
1216 .enable_reg = 0x7100c,
1217 .enable_mask = BIT(0),
1226 .halt_reg = 0x71018,
1229 .enable_reg = 0x71018,
1230 .enable_mask = BIT(0),
1239 .halt_reg = 0x4d008,
1242 .enable_reg = 0x4d008,
1243 .enable_mask = BIT(0),
1252 .halt_reg = 0x73008,
1255 .enable_reg = 0x73008,
1256 .enable_mask = BIT(0),
1265 .halt_reg = 0x73018,
1268 .enable_reg = 0x73018,
1269 .enable_mask = BIT(0),
1278 .halt_reg = 0x7301c,
1281 .enable_reg = 0x7301c,
1282 .enable_mask = BIT(0),
1291 .halt_reg = 0x4d004,
1293 .hwcg_reg = 0x4d004,
1296 .enable_reg = 0x4d004,
1297 .enable_mask = BIT(0),
1306 .halt_reg = 0x4d1a0,
1308 .hwcg_reg = 0x4d1a0,
1311 .enable_reg = 0x4d1a0,
1312 .enable_mask = BIT(0),
1323 .enable_reg = 0x52000,
1339 .enable_reg = 0x52000,
1354 .halt_reg = 0x3300c,
1357 .enable_reg = 0x3300c,
1358 .enable_mask = BIT(0),
1372 .halt_reg = 0x33004,
1374 .hwcg_reg = 0x33004,
1377 .enable_reg = 0x33004,
1378 .enable_mask = BIT(0),
1387 .halt_reg = 0x33008,
1390 .enable_reg = 0x33008,
1391 .enable_mask = BIT(0),
1400 .halt_reg = 0x34004,
1402 .hwcg_reg = 0x34004,
1405 .enable_reg = 0x52000,
1415 .halt_reg = 0x4b004,
1417 .hwcg_reg = 0x4b004,
1420 .enable_reg = 0x4b004,
1421 .enable_mask = BIT(0),
1430 .halt_reg = 0x4b008,
1433 .enable_reg = 0x4b008,
1434 .enable_mask = BIT(0),
1448 .halt_reg = 0x17014,
1451 .enable_reg = 0x52008,
1461 .halt_reg = 0x1700c,
1464 .enable_reg = 0x52008,
1474 .halt_reg = 0x17030,
1477 .enable_reg = 0x52008,
1492 .halt_reg = 0x17160,
1495 .enable_reg = 0x52008,
1510 .halt_reg = 0x17290,
1513 .enable_reg = 0x52008,
1528 .halt_reg = 0x173c0,
1531 .enable_reg = 0x52008,
1546 .halt_reg = 0x174f0,
1549 .enable_reg = 0x52008,
1564 .halt_reg = 0x17620,
1567 .enable_reg = 0x52008,
1582 .halt_reg = 0x18004,
1585 .enable_reg = 0x52008,
1595 .halt_reg = 0x18008,
1598 .enable_reg = 0x52008,
1608 .halt_reg = 0x18014,
1611 .enable_reg = 0x52008,
1626 .halt_reg = 0x18144,
1629 .enable_reg = 0x52008,
1644 .halt_reg = 0x18274,
1647 .enable_reg = 0x52008,
1662 .halt_reg = 0x183a4,
1665 .enable_reg = 0x52008,
1680 .halt_reg = 0x184d4,
1683 .enable_reg = 0x52008,
1698 .halt_reg = 0x18604,
1701 .enable_reg = 0x52008,
1716 .halt_reg = 0x17004,
1719 .enable_reg = 0x52008,
1729 .halt_reg = 0x17008,
1731 .hwcg_reg = 0x17008,
1734 .enable_reg = 0x52008,
1744 .halt_reg = 0x1800c,
1747 .enable_reg = 0x52008,
1757 .halt_reg = 0x18010,
1759 .hwcg_reg = 0x18010,
1762 .enable_reg = 0x52008,
1772 .halt_reg = 0x12008,
1775 .enable_reg = 0x12008,
1776 .enable_mask = BIT(0),
1785 .halt_reg = 0x1200c,
1788 .enable_reg = 0x1200c,
1789 .enable_mask = BIT(0),
1803 .halt_reg = 0x12040,
1806 .enable_reg = 0x12040,
1807 .enable_mask = BIT(0),
1821 .halt_reg = 0x14008,
1824 .enable_reg = 0x14008,
1825 .enable_mask = BIT(0),
1834 .halt_reg = 0x14004,
1837 .enable_reg = 0x14004,
1838 .enable_mask = BIT(0),
1853 .halt_reg = 0x4144,
1856 .enable_reg = 0x52000,
1857 .enable_mask = BIT(0),
1871 .halt_reg = 0x8c000,
1874 .enable_reg = 0x8c000,
1875 .enable_mask = BIT(0),
1884 .halt_reg = 0x77014,
1886 .hwcg_reg = 0x77014,
1889 .enable_reg = 0x77014,
1890 .enable_mask = BIT(0),
1899 .halt_reg = 0x77038,
1901 .hwcg_reg = 0x77038,
1904 .enable_reg = 0x77038,
1905 .enable_mask = BIT(0),
1919 .halt_reg = 0x77090,
1921 .hwcg_reg = 0x77090,
1924 .enable_reg = 0x77090,
1925 .enable_mask = BIT(0),
1939 .halt_reg = 0x77094,
1941 .hwcg_reg = 0x77094,
1944 .enable_reg = 0x77094,
1945 .enable_mask = BIT(0),
1959 .halt_reg = 0x7701c,
1962 .enable_reg = 0x7701c,
1963 .enable_mask = BIT(0),
1972 .halt_reg = 0x77018,
1975 .enable_reg = 0x77018,
1976 .enable_mask = BIT(0),
1985 .halt_reg = 0x7708c,
1987 .hwcg_reg = 0x7708c,
1990 .enable_reg = 0x7708c,
1991 .enable_mask = BIT(0),
2005 .halt_reg = 0xf010,
2008 .enable_reg = 0xf010,
2009 .enable_mask = BIT(0),
2023 .halt_reg = 0xf018,
2026 .enable_reg = 0xf018,
2027 .enable_mask = BIT(0),
2042 .halt_reg = 0xf014,
2045 .enable_reg = 0xf014,
2046 .enable_mask = BIT(0),
2055 .halt_reg = 0x8c010,
2058 .enable_reg = 0x8c010,
2059 .enable_mask = BIT(0),
2068 .halt_reg = 0xf050,
2071 .enable_reg = 0xf050,
2072 .enable_mask = BIT(0),
2086 .halt_reg = 0xf054,
2089 .enable_reg = 0xf054,
2090 .enable_mask = BIT(0),
2104 .halt_reg = 0xf058,
2107 .enable_reg = 0xf058,
2108 .enable_mask = BIT(0),
2117 .halt_reg = 0x6a004,
2119 .hwcg_reg = 0x6a004,
2122 .enable_reg = 0x6a004,
2123 .enable_mask = BIT(0),
2132 .halt_reg = 0xb01c,
2135 .enable_reg = 0xb01c,
2136 .enable_mask = BIT(0),
2147 .enable_reg = 0x52000,
2162 .halt_reg = 0xb07c,
2164 .hwcg_reg = 0xb07c,
2167 .enable_reg = 0xb07c,
2168 .enable_mask = BIT(0),
2177 .halt_reg = 0xb028,
2180 .enable_reg = 0xb028,
2181 .enable_mask = BIT(0),
2190 .halt_reg = 0x8a000,
2193 .enable_reg = 0x8a000,
2194 .enable_mask = BIT(0),
2203 .halt_reg = 0x8a004,
2206 .enable_reg = 0x8a004,
2207 .enable_mask = BIT(0),
2216 .halt_reg = 0x8a00c,
2219 .enable_reg = 0x8a00c,
2220 .enable_mask = BIT(0),
2229 .halt_reg = 0x8a150,
2232 .enable_reg = 0x8a150,
2233 .enable_mask = BIT(0),
2242 .halt_reg = 0x8a154,
2245 .enable_reg = 0x8a154,
2246 .enable_mask = BIT(0),
2255 .halt_reg = 0x47018,
2258 .enable_reg = 0x47018,
2259 .enable_mask = BIT(0),
2268 .gdscr = 0x77004,
2276 .gdscr = 0x0f004,
2284 .gdscr = 0x7d040,
2293 .gdscr = 0x7d044,
2448 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2449 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
2450 [GCC_UFS_PHY_BCR] = { 0x77000 },
2451 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2452 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2453 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
2454 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2455 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2456 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
2457 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2458 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2480 .max_register = 0x18208c,
2515 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); in gcc_sc7180_probe()
2516 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sc7180_probe()
2517 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sc7180_probe()
2524 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); in gcc_sc7180_probe()
2525 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); in gcc_sc7180_probe()
2526 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); in gcc_sc7180_probe()
2527 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sc7180_probe()