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Searched +full:0 +full:x18000000 (Results 1 – 19 of 19) sorted by relevance

/qemu/tests/tcg/openrisc/
H A Dtest_logic.c8 b = 0x9743; in main()
9 c = 0x2; in main()
10 result = 0x25d0c; in main()
12 ("l.sll %0, %1, %2\n\t" in main()
21 b = 0x9743; in main()
22 result = 0x25d0c; in main()
24 ("l.slli %0, %1, 0x2\n\t" in main()
33 b = 0x7654; in main()
34 c = 0x03; in main()
35 result = 0xeca; in main()
[all …]
/qemu/hw/arm/
H A Dstrongarm.h7 #define SA_CS0 0x00000000
8 #define SA_CS1 0x08000000
9 #define SA_CS2 0x10000000
10 #define SA_CS3 0x18000000
11 #define SA_PCMCIA_CS0 0x20000000
12 #define SA_PCMCIA_CS1 0x30000000
13 #define SA_CS4 0x40000000
14 #define SA_CS5 0x48000000
16 #define SA_SDCS0 0xc0000000
17 #define SA_SDCS1 0xc8000000
[all …]
H A Dvexpress.c50 #define VEXPRESS_BOARD_ID 0x8e0
56 /* Number of virtio transports to create (0..8; limited by
100 [VE_NORFLASHALIAS] = 0,
101 /* CS7: 0x10000000 .. 0x10020000 */
102 [VE_SYSREGS] = 0x10000000,
103 [VE_SP810] = 0x10001000,
104 [VE_SERIALPCI] = 0x10002000,
105 [VE_PL041] = 0x10004000,
106 [VE_MMCI] = 0x10005000,
107 [VE_KMI0] = 0x10006000,
[all …]
H A Dintegratorcp.c58 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
59 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
86 if (offset >= 0x100 && offset < 0x200) { in integratorcm_read()
88 if (offset >= 0x180) in integratorcm_read()
89 return 0; in integratorcm_read()
93 case 0: /* CM_ID */ in integratorcm_read()
94 return 0x411a3001; in integratorcm_read()
96 return 0; in integratorcm_read()
102 return 0x00100000; in integratorcm_read()
104 if (s->cm_lock == 0xa05f) { in integratorcm_read()
[all …]
H A Daspeed_ast2600.c21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000
25 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
26 [ASPEED_DEV_SRAM] = 0x10000000,
27 [ASPEED_DEV_DPMCU] = 0x18000000,
28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
29 [ASPEED_DEV_IOMEM] = 0x1E600000,
30 [ASPEED_DEV_PWM] = 0x1E610000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
[all …]
H A Dfsl-imx8mp.c29 [FSL_IMX8MP_DDR_PHY_BROADCAST] = { 0x3dc00000, 4 * MiB, "ddr_phy_broadcast" },
30 [FSL_IMX8MP_DDR_PERF_MON] = { 0x3d800000, 4 * MiB, "ddr_perf_mon" },
31 [FSL_IMX8MP_DDR_CTL] = { 0x3d400000, 4 * MiB, "ddr_ctl" },
32 [FSL_IMX8MP_DDR_BLK_CTRL] = { 0x3d000000, 1 * MiB, "ddr_blk_ctrl" },
33 [FSL_IMX8MP_DDR_PHY] = { 0x3c000000, 16 * MiB, "ddr_phy" },
34 [FSL_IMX8MP_AUDIO_DSP] = { 0x3b000000, 16 * MiB, "audio_dsp" },
35 [FSL_IMX8MP_GIC_DIST] = { 0x38800000, 512 * KiB, "gic_dist" },
36 [FSL_IMX8MP_GIC_REDIST] = { 0x38880000, 512 * KiB, "gic_redist" },
37 [FSL_IMX8MP_NPU] = { 0x38500000, 2 * MiB, "npu" },
38 [FSL_IMX8MP_VPU] = { 0x38340000, 2 * MiB, "vpu" },
[all …]
/qemu/tests/qtest/libqos/
H A Dloongarch-virt-machine.c28 #define LOONGARCH_PAGE_SIZE 0x1000
29 #define LOONGARCH_VIRT_RAM_ADDR 0x100000
30 #define LOONGARCH_VIRT_RAM_SIZE 0xFF00000
32 #define LOONGARCH_VIRT_PIO_BASE 0x18000000
33 #define LOONGARCH_VIRT_PCIE_PIO_OFFSET 0x4000
34 #define LOONGARCH_VIRT_PCIE_PIO_LIMIT 0x10000
35 #define LOONGARCH_VIRT_PCIE_ECAM_BASE 0x20000000
36 #define LOONGARCH_VIRT_PCIE_MMIO32_BASE 0x40000000
37 #define LOONGARCH_VIRT_PCIE_MMIO32_LIMIT 0x80000000
92 alloc_init(&machine->alloc, 0, in qos_create_machine_loongarch_virt()
/qemu/hw/mips/
H A Dmalta.c65 #define ENVP_PADDR 0x2000
71 #define FLASH_ADDRESS 0x1e000000ULL
72 #define FPGA_ADDRESS 0x1f000000ULL
73 #define RESET_ADDRESS 0x1fc00000ULL
75 #define FLASH_SIZE 0x400000
78 #define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
82 MemoryRegion iomem_lo; /* 0 - 0x900 */
83 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
120 for (i = 7 ; i >= 0 ; i--) { in malta_fpga_update_display_leds()
127 leds_text[8] = '\0'; in malta_fpga_update_display_leds()
[all …]
H A Dloongson3_virt.c54 #define PM_CNTL_MODE 0x10
65 #define UART_IRQ 0
70 [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
71 [VIRT_PM] = { 0x10080000, 0x100 },
72 [VIRT_FW_CFG] = { 0x10080100, 0x100 },
73 [VIRT_RTC] = { 0x10081000, 0x1000 },
74 [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 },
75 [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
76 [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
77 [VIRT_UART] = { 0x1fe001e0, 0x8 },
[all …]
H A Dboston.c54 #define FDT_IRQ_TYPE_NONE 0
56 #define FDT_GIC_SHARED 0
99 [BOSTON_LOWDDR] = { 0x0, 0x10000000 },
100 [BOSTON_PCIE0] = { 0x10000000, 0x2000000 },
101 [BOSTON_PCIE1] = { 0x12000000, 0x2000000 },
102 [BOSTON_PCIE2] = { 0x14000000, 0x2000000 },
103 [BOSTON_PCIE2_MMIO] = { 0x16000000, 0x100000 },
104 [BOSTON_CM] = { 0x16100000, 0x20000 },
105 [BOSTON_GIC] = { 0x16120000, 0x20000 },
106 [BOSTON_CDMM] = { 0x16140000, 0x8000 },
[all …]
/qemu/contrib/plugins/
H A Dhowvec.c25 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
62 * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0
66 { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE},
67 { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS},
68 { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS},
70 { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS},
71 { " Add/Sub (imm,tags)", "asit", 0x1f800000, 0x11800000, COUNT_CLASS},
72 { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS},
73 { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS},
74 { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS},
[all …]
/qemu/hw/pci-host/
H A Dbonito.c28 * VT686B_FUN0's devfn = (5<<3)+0
66 #define BONITO_BOOT_BASE 0x1fc00000
67 #define BONITO_BOOT_SIZE 0x00100000
69 #define BONITO_FLASH_BASE 0x1c000000
70 #define BONITO_FLASH_SIZE 0x03000000
72 #define BONITO_SOCKET_BASE 0x1f800000
73 #define BONITO_SOCKET_SIZE 0x00400000
75 #define BONITO_REG_BASE 0x1fe00000
76 #define BONITO_REG_SIZE 0x00040000
78 #define BONITO_DEV_BASE 0x1ff00000
[all …]
/qemu/target/sh4/
H A Dhelper.c33 #define MMU_OK 0
53 return !(addr & 0x80000000); in cpu_sh4_is_cached()
70 if (do_exp && cs->exception_index != 0x1e0) { in superh_cpu_do_interrupt()
84 env->in_sleep = 0; in superh_cpu_do_interrupt()
88 (env->sr >> 4) & 0xf); in superh_cpu_do_interrupt()
97 case 0x0e0: in superh_cpu_do_interrupt()
100 case 0x040: in superh_cpu_do_interrupt()
103 case 0x0a0: in superh_cpu_do_interrupt()
106 case 0x180: in superh_cpu_do_interrupt()
109 case 0x1a0: in superh_cpu_do_interrupt()
[all …]
/qemu/linux-user/
H A Dmain.c66 #define AT_FLAGS_PRESERVE_ARGV0_BIT 0
115 # define MAX_RESERVED_VA(CPU) 0xfffffffful
120 # define MAX_RESERVED_VA(CPU) 0
156 bool child = pid == 0; in fork_end()
197 if (ts->ts_tid == 0) { in task_settid()
219 .ss_sp = 0, in init_task_state()
220 .ss_size = 0, in init_task_state()
228 if ((ticks_per_sec > 0) && !clock_gettime(CLOCK_BOOTTIME, &bt)) { in init_task_state()
249 new_env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, in cpu_copy()
251 MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); in cpu_copy()
[all …]
/qemu/disas/
H A Dmicroblaze.c137 /* gen purpose regs go from 0 to 31 */
140 #define REG_PC_MASK 0x8000
141 #define REG_MSR_MASK 0x8001
142 #define REG_EAR_MASK 0x8003
143 #define REG_ESR_MASK 0x8005
144 #define REG_FSR_MASK 0x8007
145 #define REG_BTR_MASK 0x800b
146 #define REG_EDR_MASK 0x800d
147 #define REG_PVR_MASK 0xa000
149 #define REG_PID_MASK 0x9000
[all …]
H A Dmips.c82 #define OP_MASK_OP 0x3f
84 #define OP_MASK_RS 0x1f
86 #define OP_MASK_FR 0x1f
88 #define OP_MASK_FMT 0x1f
90 #define OP_MASK_BCC 0x7
92 #define OP_MASK_CODE 0x3ff
94 #define OP_MASK_CODE2 0x3ff
96 #define OP_MASK_RT 0x1f
98 #define OP_MASK_FT 0x1f
100 #define OP_MASK_CACHE 0x1f
[all …]
H A Dhppa.c50 #define PA_PAGESIZE 0x1000
59 R_HPPA_FSEL = 0x0,
60 R_HPPA_LSSEL = 0x1,
61 R_HPPA_RSSEL = 0x2,
62 R_HPPA_LSEL = 0x3,
63 R_HPPA_RSEL = 0x4,
64 R_HPPA_LDSEL = 0x5,
65 R_HPPA_RDSEL = 0x6,
66 R_HPPA_LRSEL = 0x7,
67 R_HPPA_RRSEL = 0x8,
[all …]
/qemu/hw/sh4/
H A Dsh7750_regs.h42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
45 #define SH7750_P4_BASE 0xff000000 /* Accessible only in privileged mode */
46 #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */
56 #define SH7750_PTEH_REGOFS 0x000000 /* offset */
59 #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */
61 #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */
62 #define SH7750_PTEH_ASID_S 0
65 #define SH7750_PTEL_REGOFS 0x000004 /* offset */
68 #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */
[all …]
/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc12 OPC_MOVGR2SCR = 0x00000800,
13 OPC_MOVSCR2GR = 0x00000c00,
14 OPC_CLZ_W = 0x00001400,
15 OPC_CTZ_W = 0x00001c00,
16 OPC_CLZ_D = 0x00002400,
17 OPC_CTZ_D = 0x00002c00,
18 OPC_REVB_2H = 0x00003000,
19 OPC_REVB_2W = 0x00003800,
20 OPC_REVB_D = 0x00003c00,
21 OPC_SEXT_H = 0x00005800,
[all …]