Lines Matching +full:0 +full:x18000000
28 * VT686B_FUN0's devfn = (5<<3)+0
66 #define BONITO_BOOT_BASE 0x1fc00000
67 #define BONITO_BOOT_SIZE 0x00100000
69 #define BONITO_FLASH_BASE 0x1c000000
70 #define BONITO_FLASH_SIZE 0x03000000
72 #define BONITO_SOCKET_BASE 0x1f800000
73 #define BONITO_SOCKET_SIZE 0x00400000
75 #define BONITO_REG_BASE 0x1fe00000
76 #define BONITO_REG_SIZE 0x00040000
78 #define BONITO_DEV_BASE 0x1ff00000
79 #define BONITO_DEV_SIZE 0x00100000
81 #define BONITO_PCILO_BASE 0x10000000
82 #define BONITO_PCILO_BASE_VA 0xb0000000
83 #define BONITO_PCILO_SIZE 0x0c000000
85 #define BONITO_PCILO0_BASE 0x10000000
86 #define BONITO_PCILO1_BASE 0x14000000
87 #define BONITO_PCILO2_BASE 0x18000000
88 #define BONITO_PCIHI_BASE 0x20000000
89 #define BONITO_PCIHI_SIZE 0x60000000
91 #define BONITO_PCIIO_BASE 0x1fd00000
92 #define BONITO_PCIIO_BASE_VA 0xbfd00000
93 #define BONITO_PCIIO_SIZE 0x00010000
95 #define BONITO_PCICFG_BASE 0x1fe80000
96 #define BONITO_PCICFG_SIZE 0x00080000
100 #define BONITO_PCICONFIGBASE 0x00
101 #define BONITO_REGBASE 0x100
104 #define BONITO_PCICONFIG_SIZE (0x100)
107 #define BONITO_INTERNAL_REG_SIZE (0x70)
117 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */
120 #define BONITO_BONGENCFG_OFFSET 0x4
121 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */
122 REG32(BONGENCFG, 0x104)
123 FIELD(BONGENCFG, DEBUGMODE, 0, 1)
133 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */
136 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */
139 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */
140 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */
141 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */
145 #define BONITO_GPIODATA_OFFSET 0x1c
146 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */
147 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */
150 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */
151 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */
152 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */
155 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */
156 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */
157 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */
158 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */
161 #define BONITO_PCIMAIL0_OFFSET 0x40
162 #define BONITO_PCIMAIL1_OFFSET 0x44
163 #define BONITO_PCIMAIL2_OFFSET 0x48
164 #define BONITO_PCIMAIL3_OFFSET 0x4c
165 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */
166 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */
167 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */
168 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */
171 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */
172 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */
173 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */
174 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */
177 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */
178 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */
179 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */
180 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */
182 #define BONITO_REGS (0x70 >> 2)
184 /* PCI config for south bridge. type 0 */
185 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */
187 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */
190 #define BONITO_PCICONF_REG_MASK_HW 0xff /* As seen running PMON */
191 #define BONITO_PCICONF_REG_OFFSET 0
250 int reset = 0; in OBJECT_DECLARE_SIMPLE_TYPE()
283 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { in OBJECT_DECLARE_SIMPLE_TYPE()
284 reset = 1; /* bit 2 jump from 0 to 1 cause reset */ in OBJECT_DECLARE_SIMPLE_TYPE()
357 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
376 return 0; in bonito_ldma_readl()
393 ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff; in bonito_ldma_writel()
413 return 0; in bonito_cop_readl()
430 ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff; in bonito_cop_writel()
455 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { in bonito_sbridge_pciaddr()
456 return 0xffffffff; in bonito_sbridge_pciaddr()
459 cfgaddr = addr & 0xffff; in bonito_sbridge_pciaddr()
460 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; in bonito_sbridge_pciaddr()
468 if (idsel == 0) { in bonito_sbridge_pciaddr()
469 error_report("error in bonito pci config address 0x" HWADDR_FMT_plx in bonito_sbridge_pciaddr()
470 ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]); in bonito_sbridge_pciaddr()
494 if (pciaddr == 0xffffffff) { in bonito_spciconf_write()
523 if (pciaddr == 0xffffffff) { in bonito_spciconf_read()
524 return MAKE_64BIT_MASK(0, size * 8); in bonito_spciconf_read()
541 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
572 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
596 uint32_t val = 0; in bonito_reset_hold()
600 s->regs[BONITO_BONPONCFG] = 0xc40; in bonito_reset_hold()
608 s->regs[BONITO_IODEVCFG] = 0x2bff8010; in bonito_reset_hold()
609 s->regs[BONITO_SDCFG] = 0x255e0091; in bonito_reset_hold()
611 s->regs[BONITO_GPIODATA] = 0x1ff; in bonito_reset_hold()
612 s->regs[BONITO_GPIOIE] = 0x1ff; in bonito_reset_hold()
613 s->regs[BONITO_DQCFG] = 0x8; in bonito_reset_hold()
614 s->regs[BONITO_MEMSIZE] = 0x10000000; in bonito_reset_hold()
615 s->regs[BONITO_PCIMAP] = 0x6140; in bonito_reset_hold()
638 PCI_DEVFN(5, 0), 32, TYPE_PCI_BUS); in bonito_host_realize()
640 for (size_t i = 0; i < 3; i++) { in bonito_host_realize()
666 pci_config_set_prog_interface(dev->config, 0x00); in bonito_pci_realize()
688 "ldma", 0x100); in bonito_pci_realize()
689 memory_region_add_subregion(host_mem, 0x1fe00200, &s->iomem_ldma); in bonito_pci_realize()
693 "cop", 0x100); in bonito_pci_realize()
694 memory_region_add_subregion(host_mem, 0x1fe00300, &s->iomem_cop); in bonito_pci_realize()
698 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ in bonito_pci_realize()
700 get_system_io(), 0, BONITO_PCIIO_SIZE); in bonito_pci_realize()
706 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]", in bonito_pci_realize()
707 get_system_io(), 0, 256 * KiB); in bonito_pci_realize()
718 &bs->pci_mem, 0, BONITO_PCIHI_SIZE); in bonito_pci_realize()
725 pci_set_word(dev->config + PCI_COMMAND, 0x0000); in bonito_pci_realize()
726 pci_set_word(dev->config + PCI_STATUS, 0x0000); in bonito_pci_realize()
727 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); in bonito_pci_realize()
728 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); in bonito_pci_realize()
730 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); in bonito_pci_realize()
731 pci_config_set_interrupt_pin(dev->config, 0x01); /* interrupt pin A */ in bonito_pci_realize()
733 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); in bonito_pci_realize()
734 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); in bonito_pci_realize()
751 d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO); in bonito_init()
768 k->vendor_id = 0xdf53; in bonito_pci_class_init()
769 k->device_id = 0x00d5; in bonito_pci_class_init()
770 k->revision = 0x01; in bonito_pci_class_init()