50 #define VEXPRESS_BOARD_ID 0x8e0
56 /* Number of virtio transports to create (0..8; limited by
100     [VE_NORFLASHALIAS] = 0,
101     /* CS7: 0x10000000 .. 0x10020000 */
102     [VE_SYSREGS] = 0x10000000,
103     [VE_SP810] = 0x10001000,
104     [VE_SERIALPCI] = 0x10002000,
105     [VE_PL041] = 0x10004000,
106     [VE_MMCI] = 0x10005000,
107     [VE_KMI0] = 0x10006000,
108     [VE_KMI1] = 0x10007000,
109     [VE_UART0] = 0x10009000,
110     [VE_UART1] = 0x1000a000,
111     [VE_UART2] = 0x1000b000,
112     [VE_UART3] = 0x1000c000,
113     [VE_WDT] = 0x1000f000,
114     [VE_TIMER01] = 0x10011000,
115     [VE_TIMER23] = 0x10012000,
116     [VE_VIRTIO] = 0x10013000,
117     [VE_SERIALDVI] = 0x10016000,
118     [VE_RTC] = 0x10017000,
119     [VE_COMPACTFLASH] = 0x1001a000,
120     [VE_CLCD] = 0x1001f000,
121     /* CS0: 0x40000000 .. 0x44000000 */
122     [VE_NORFLASH0] = 0x40000000,
123     /* CS1: 0x44000000 .. 0x48000000 */
124     [VE_NORFLASH1] = 0x44000000,
125     /* CS2: 0x48000000 .. 0x4a000000 */
126     [VE_SRAM] = 0x48000000,
127     /* CS3: 0x4c000000 .. 0x50000000 */
128     [VE_VIDEORAM] = 0x4c000000,
129     [VE_ETHERNET] = 0x4e000000,
130     [VE_USB] = 0x4f000000,
134     [VE_NORFLASHALIAS] = 0,
135     /* CS0: 0x08000000 .. 0x0c000000 */
136     [VE_NORFLASH0] = 0x08000000,
137     /* CS4: 0x0c000000 .. 0x10000000 */
138     [VE_NORFLASH1] = 0x0c000000,
139     /* CS5: 0x10000000 .. 0x14000000 */
140     /* CS1: 0x14000000 .. 0x18000000 */
141     [VE_SRAM] = 0x14000000,
142     /* CS2: 0x18000000 .. 0x1c000000 */
143     [VE_VIDEORAM] = 0x18000000,
144     [VE_ETHERNET] = 0x1a000000,
145     [VE_USB] = 0x1b000000,
146     /* CS3: 0x1c000000 .. 0x20000000 */
147     [VE_DAPROM] = 0x1c000000,
148     [VE_SYSREGS] = 0x1c010000,
149     [VE_SP810] = 0x1c020000,
150     [VE_SERIALPCI] = 0x1c030000,
151     [VE_PL041] = 0x1c040000,
152     [VE_MMCI] = 0x1c050000,
153     [VE_KMI0] = 0x1c060000,
154     [VE_KMI1] = 0x1c070000,
155     [VE_UART0] = 0x1c090000,
156     [VE_UART1] = 0x1c0a0000,
157     [VE_UART2] = 0x1c0b0000,
158     [VE_UART3] = 0x1c0c0000,
159     [VE_WDT] = 0x1c0f0000,
160     [VE_TIMER01] = 0x1c110000,
161     [VE_TIMER23] = 0x1c120000,
162     [VE_VIRTIO] = 0x1c130000,
163     [VE_SERIALDVI] = 0x1c160000,
164     [VE_RTC] = 0x1c170000,
165     [VE_COMPACTFLASH] = 0x1c1a0000,
166     [VE_CLCD] = 0x1c1f0000,
221     for (n = 0; n < smp_cpus; n++) {  in init_cpus()
249     sysbus_mmio_map(busdev, 0, periphbase);  in init_cpus()
251     /* Interrupts [42:0] are from the motherboard;  in init_cpus()
255      * are internal interrupts 0..31).  in init_cpus()
257     for (n = 0; n < GIC_EXT_IRQS; n++) {  in init_cpus()
262     for (n = 0; n < smp_cpus; n++) {  in init_cpus()
284     if (ram_size > 0x40000000) {  in a9_daughterboard_init()
291      * RAM is from 0x60000000 upwards. The bottom 64MB of the  in a9_daughterboard_init()
295     memory_region_add_subregion(sysmem, 0x60000000, machine->ram);  in a9_daughterboard_init()
297     /* 0x1e000000 A9MPCore (SCU) private memory region */  in a9_daughterboard_init()
298     init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,  in a9_daughterboard_init()
301     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */  in a9_daughterboard_init()
303     /* 0x10020000 PL111 CLCD (daughterboard) */  in a9_daughterboard_init()
308     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10020000);  in a9_daughterboard_init()
309     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[44]);  in a9_daughterboard_init()
311     /* 0x10060000 AXI RAM */  in a9_daughterboard_init()
312     /* 0x100e0000 PL341 Dynamic Memory Controller */  in a9_daughterboard_init()
313     /* 0x100e1000 PL354 Static Memory Controller */  in a9_daughterboard_init()
314     /* 0x100e2000 System Configuration Controller */  in a9_daughterboard_init()
316     sysbus_create_simple("sp804", 0x100e4000, pic[48]);  in a9_daughterboard_init()
317     /* 0x100e5000 SP805 Watchdog module */  in a9_daughterboard_init()
318     /* 0x100e6000 BP147 TrustZone Protection Controller */  in a9_daughterboard_init()
319     /* 0x100e9000 PL301 'Fast' AXI matrix */  in a9_daughterboard_init()
320     /* 0x100ea000 PL301 'Slow' AXI matrix */  in a9_daughterboard_init()
321     /* 0x100ec000 TrustZone Address Space Controller */  in a9_daughterboard_init()
322     /* 0x10200000 CoreSight debug APB */  in a9_daughterboard_init()
323     /* 0x1e00a000 PL310 L2 Cache Controller */  in a9_daughterboard_init()
324     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);  in a9_daughterboard_init()
348     .loader_start = 0x60000000,
349     .gic_cpu_if_addr = 0x1e000100,
350     .proc_id = 0x0c000191,
378     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */  in a15_daughterboard_init()
379     memory_region_add_subregion(sysmem, 0x80000000, machine->ram);  in a15_daughterboard_init()
381     /* 0x2c000000 A15MPCore private memory region (GIC) */  in a15_daughterboard_init()
383               0x2c000000, pic, vms->secure, vms->virt);  in a15_daughterboard_init()
387     /* 0x20000000: CoreSight interfaces: not modelled */  in a15_daughterboard_init()
388     /* 0x2a000000: PL301 AXI interconnect: not modelled */  in a15_daughterboard_init()
389     /* 0x2a420000: SCC: not modelled */  in a15_daughterboard_init()
390     /* 0x2a430000: system counter: not modelled */  in a15_daughterboard_init()
391     /* 0x2b000000: HDLCD controller: not modelled */  in a15_daughterboard_init()
392     /* 0x2b060000: SP805 watchdog: not modelled */  in a15_daughterboard_init()
393     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */  in a15_daughterboard_init()
394     /* 0x2e000000: system SRAM */  in a15_daughterboard_init()
395     memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000,  in a15_daughterboard_init()
397     memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram);  in a15_daughterboard_init()
399     /* 0x7ffb0000: DMA330 DMA controller: not modelled */  in a15_daughterboard_init()
400     /* 0x7ffd0000: PL354 static memory controller: not modelled */  in a15_daughterboard_init()
409     0, /* OSCCLK1: reserved */
410     0, /* OSCCLK2: reserved */
411     0, /* OSCCLK3: reserved */
421     .loader_start = 0x80000000,
422     .gic_cpu_if_addr = 0x2c002000,
423     .proc_id = 0x14000237,
440      *       interrupts = <0, irq, 1>;  in add_virtio_mmio_node()
455     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);  in add_virtio_mmio_node()
456     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);  in add_virtio_mmio_node()
461     return 0;  in add_virtio_mmio_node()
470      * We return the phandle of the node, or 0 if none was found.  in find_int_controller()
476     if (offset >= 0) {  in find_int_controller()
479     return 0;  in find_int_controller()
505         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {  in vexpress_modify_dtb()
507                                  map[VE_VIRTIO] + 0x200 * i,  in vexpress_modify_dtb()
508                                  0x200, intc, 40 + i);  in vexpress_modify_dtb()
532     qdev_prop_set_uint16(dev, "id0", 0x89);  in ve_pflash_cfi01_register()
533     qdev_prop_set_uint16(dev, "id1", 0x18);  in ve_pflash_cfi01_register()
534     qdev_prop_set_uint16(dev, "id2", 0x00);  in ve_pflash_cfi01_register()
535     qdev_prop_set_uint16(dev, "id3", 0x00);  in ve_pflash_cfi01_register()
539     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);  in ve_pflash_cfi01_register()
569         if (drive_get(IF_PFLASH, 0, 0)) {  in vexpress_common_init()
583         if (image_size < 0) {  in vexpress_common_init()
593     sys_id = 0x1190f500;  in vexpress_common_init()
600     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {  in vexpress_common_init()
606     for (i = 0; i < daughterboard->num_clocks; i++) {  in vexpress_common_init()
612     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);  in vexpress_common_init()
623     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);  in vexpress_common_init()
624     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);  in vexpress_common_init()
628     qdev_connect_gpio_out_named(dev, "card-read-only", 0,  in vexpress_common_init()
630     qdev_connect_gpio_out_named(dev, "card-inserted", 0,  in vexpress_common_init()
632     dinfo = drive_get(IF_SD, 0, 0);  in vexpress_common_init()
646     pl011_create(map[VE_UART0], pic[5], serial_hd(0));  in vexpress_common_init()
656     i2c_slave_create_simple(i2c, "sii9022", 0x39);  in vexpress_common_init()
666     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, map[VE_CLCD]);  in vexpress_common_init()
667     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[14]);  in vexpress_common_init()
669     dinfo = drive_get(IF_PFLASH, 0, 0);  in vexpress_common_init()
674         /* Map flash 0 as an alias into low memory */  in vexpress_common_init()
676         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);  in vexpress_common_init()
678                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);  in vexpress_common_init()
682     dinfo = drive_get(IF_PFLASH, 0, 1);  in vexpress_common_init()
685     sram_size = 0x2000000;  in vexpress_common_init()
690     vram_size = 0x800000;  in vexpress_common_init()
695     /* 0x4e000000 LAN9118 Ethernet */  in vexpress_common_init()
708     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {  in vexpress_common_init()
709         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,  in vexpress_common_init()
717     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;  in vexpress_common_init()