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/qemu/include/hw/arm/
H A Dnrf51.h6 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
18 #define NRF51_FLASH_BASE 0x00000000
19 #define NRF51_FICR_BASE 0x10000000
20 #define NRF51_FICR_SIZE 0x00000100
21 #define NRF51_UICR_BASE 0x10001000
22 #define NRF51_SRAM_BASE 0x20000000
24 #define NRF51_IOMEM_BASE 0x40000000
25 #define NRF51_IOMEM_SIZE 0x20000000
27 #define NRF51_PERIPHERAL_SIZE 0x00001000
28 #define NRF51_UART_BASE 0x40002000
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/qemu/hw/arm/
H A Dversatilepb.c32 #define VERSATILE_FLASH_ADDR 0x34000000
69 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
81 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
103 case 0: /* STATUS */ in vpb_sic_read()
115 "vpb_sic_read: Bad register offset 0x%x\n", (int)offset); in vpb_sic_read()
116 return 0; in vpb_sic_read()
141 s->pic_enable |= (value & 0x7fe00000); in vpb_sic_write()
150 "vpb_sic_write: Bad register offset 0x%x\n", (int)offset); in vpb_sic_write()
170 for (i = 0; i < 32; i++) { in vpb_sic_init()
175 "vpb-sic", 0x1000); in vpb_sic_init()
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H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
56 0x33b,
57 0x33b,
58 0x769,
59 0x76d
70 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
72 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
73 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
95 int is_mpcore = 0; in realview_init()
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H A Dvexpress.c50 #define VEXPRESS_BOARD_ID 0x8e0
56 /* Number of virtio transports to create (0..8; limited by
100 [VE_NORFLASHALIAS] = 0,
101 /* CS7: 0x10000000 .. 0x10020000 */
102 [VE_SYSREGS] = 0x10000000,
103 [VE_SP810] = 0x10001000,
104 [VE_SERIALPCI] = 0x10002000,
105 [VE_PL041] = 0x10004000,
106 [VE_MMCI] = 0x10005000,
107 [VE_KMI0] = 0x10006000,
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/qemu/hw/riscv/
H A Dvirt.c83 [VIRT_DEBUG] = { 0x0, 0x100 },
84 [VIRT_MROM] = { 0x1000, 0xf000 },
85 [VIRT_TEST] = { 0x100000, 0x1000 },
86 [VIRT_RTC] = { 0x101000, 0x1000 },
87 [VIRT_CLINT] = { 0x2000000, 0x10000 },
88 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
89 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
90 [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 },
91 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
92 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
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