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/qemu/include/hw/s390x/
H A Dioinst.h31 #define SCSW_FLAGS_MASK_KEY 0xf000
32 #define SCSW_FLAGS_MASK_SCTL 0x0800
33 #define SCSW_FLAGS_MASK_ESWF 0x0400
34 #define SCSW_FLAGS_MASK_CC 0x0300
35 #define SCSW_FLAGS_MASK_FMT 0x0080
36 #define SCSW_FLAGS_MASK_PFCH 0x0040
37 #define SCSW_FLAGS_MASK_ISIC 0x0020
38 #define SCSW_FLAGS_MASK_ALCC 0x0010
39 #define SCSW_FLAGS_MASK_SSI 0x0008
40 #define SCSW_FLAGS_MASK_ZCC 0x0004
[all …]
H A Ds390-pci-clp.h31 #define CLP_RC_OK 0x0010 /* Command request successfully */
32 #define CLP_RC_CMD 0x0020 /* Command code not recognized */
33 #define CLP_RC_PERM 0x0030 /* Command not authorized */
34 #define CLP_RC_FMT 0x0040 /* Invalid command request format */
35 #define CLP_RC_LEN 0x0050 /* Invalid command request length */
36 #define CLP_RC_8K 0x0060 /* Command requires 8K LPCB */
37 #define CLP_RC_RESNOT0 0x0070 /* Reserved field not zero */
38 #define CLP_RC_NODATA 0x0080 /* No data available */
39 #define CLP_RC_FC_UNKNOWN 0x0100 /* Function code not recognized */
44 #define CLP_LIST_PCI 0x0002
[all …]
/qemu/include/standard-headers/linux/
H A Dpci_regs.h38 #define PCI_VENDOR_ID 0x00 /* 16 bits */
39 #define PCI_DEVICE_ID 0x02 /* 16 bits */
40 #define PCI_COMMAND 0x04 /* 16 bits */
41 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
42 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
43 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
44 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
45 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
46 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
47 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
[all …]
/qemu/include/hw/acpi/
H A Dacpi.h63 #define ACPI_BITMASK_TIMER_STATUS 0x0001
64 #define ACPI_BITMASK_BUS_MASTER_STATUS 0x0010
65 #define ACPI_BITMASK_GLOBAL_LOCK_STATUS 0x0020
66 #define ACPI_BITMASK_POWER_BUTTON_STATUS 0x0100
67 #define ACPI_BITMASK_SLEEP_BUTTON_STATUS 0x0200
68 #define ACPI_BITMASK_RT_CLOCK_STATUS 0x0400
69 #define ACPI_BITMASK_PCIEXP_WAKE_STATUS 0x4000 /* ACPI 3.0 */
70 #define ACPI_BITMASK_WAKE_STATUS 0x8000
82 #define ACPI_BITMASK_TIMER_ENABLE 0x0001
83 #define ACPI_BITMASK_GLOBAL_LOCK_ENABLE 0x0020
[all …]
/qemu/hw/sd/
H A Dsdhci-internal.h2 * SD Association Host Standard Specification v2.0 controller emulation
29 /* R/W SDMA System Address register 0x0 */
30 #define SDHC_SYSAD 0x00
32 /* R/W Host DMA Buffer Boundary and Transfer Block Size Register 0x0 */
33 #define SDHC_BLKSIZE 0x04
35 /* R/W Blocks count for current transfer 0x0 */
36 #define SDHC_BLKCNT 0x06
38 /* R/W Command Argument Register 0x0 */
39 #define SDHC_ARGUMENT 0x08
41 /* R/W Transfer Mode Setting Register 0x0 */
[all …]
/qemu/include/exec/
H A Dpage-protection.h12 #define PAGE_READ 0x0001
13 #define PAGE_WRITE 0x0002
14 #define PAGE_EXEC 0x0004
16 #define PAGE_VALID 0x0008
20 #define PAGE_WRITE_ORG 0x0010
25 #define PAGE_WRITE_INV 0x0020
27 #define PAGE_RESET 0x0040
29 #define PAGE_ANON 0x0080
32 #define PAGE_TARGET_1 0x0200
33 #define PAGE_TARGET_2 0x0400
[all …]
H A Dcpu-interrupt.h13 * compatibility with the vmstate dump. Bit 0 (0x0001) was previously used
21 #define CPU_INTERRUPT_HARD 0x0002
27 #define CPU_INTERRUPT_EXITTB 0x0004
30 #define CPU_INTERRUPT_HALT 0x0020
33 #define CPU_INTERRUPT_DEBUG 0x0080
36 #define CPU_INTERRUPT_RESET 0x0400
42 #define CPU_INTERRUPT_TGT_EXT_0 0x0008
43 #define CPU_INTERRUPT_TGT_EXT_1 0x0010
44 #define CPU_INTERRUPT_TGT_EXT_2 0x0040
45 #define CPU_INTERRUPT_TGT_EXT_3 0x0200
[all …]
/qemu/linux-user/hppa/
H A Dsockbits.h4 #define TARGET_SOL_SOCKET 0xffff
6 #define TARGET_SO_DEBUG 0x0001
7 #define TARGET_SO_REUSEADDR 0x0004
8 #define TARGET_SO_KEEPALIVE 0x0008
9 #define TARGET_SO_DONTROUTE 0x0010
10 #define TARGET_SO_BROADCAST 0x0020
11 #define TARGET_SO_LINGER 0x0080
12 #define TARGET_SO_OOBINLINE 0x0100
13 #define TARGET_SO_REUSEPORT 0x0200
14 #define TARGET_SO_SNDBUF 0x1001
[all …]
/qemu/include/hw/adc/
H A Dzynq-xadc.h21 #define ZYNQ_XADC_MMIO_SIZE 0x0020
/qemu/linux-user/alpha/
H A Dsockbits.h12 #define TARGET_SOL_SOCKET 0xffff
14 #define TARGET_SO_DEBUG 0x0001
15 #define TARGET_SO_REUSEADDR 0x0004
16 #define TARGET_SO_KEEPALIVE 0x0008
17 #define TARGET_SO_DONTROUTE 0x0010
18 #define TARGET_SO_BROADCAST 0x0020
19 #define TARGET_SO_LINGER 0x0080
20 #define TARGET_SO_OOBINLINE 0x0100
21 #define TARGET_SO_REUSEPORT 0x0200
23 #define TARGET_SO_TYPE 0x1008
[all …]
/qemu/include/hw/misc/
H A Dmips_cmgcr.h19 #define GCR_BASE_ADDR 0x1fbf8000ULL
20 #define GCR_ADDRSPACE_SZ 0x8000
23 #define MIPS_GCB_OFS 0x0000 /* Global Control Block */
24 #define MIPS_CLCB_OFS 0x2000 /* Core Local Control Block */
25 #define MIPS_COCB_OFS 0x4000 /* Core Other Control Block */
26 #define MIPS_GDB_OFS 0x6000 /* Global Debug Block */
29 #define GCR_CONFIG_OFS 0x0000
30 #define GCR_BASE_OFS 0x0008
31 #define GCR_REV_OFS 0x0030
32 #define GCR_GIC_BASE_OFS 0x0080
[all …]
/qemu/linux-user/sparc/
H A Dsockbits.h12 #define TARGET_SOL_SOCKET 0xffff
14 #define TARGET_SO_DEBUG 0x0001
15 #define TARGET_SO_PASSCRED 0x0002
16 #define TARGET_SO_REUSEADDR 0x0004
17 #define TARGET_SO_KEEPALIVE 0x0008
18 #define TARGET_SO_DONTROUTE 0x0010
19 #define TARGET_SO_BROADCAST 0x0020
20 #define TARGET_SO_PEERCRED 0x0040
21 #define TARGET_SO_LINGER 0x0080
22 #define TARGET_SO_OOBINLINE 0x0100
[all …]
/qemu/pc-bios/s390-ccw/
H A Dsclp.h15 #define SCLP_CMDW_READ_SCP_INFO 0x00020001
16 #define SCLP_CMDW_READ_SCP_INFO_FORCED 0x00120001
17 #define SCLP_CMD_READ_EVENT_DATA 0x00770005
18 #define SCLP_CMD_WRITE_EVENT_DATA 0x00760005
19 #define SCLP_CMD_READ_EVENT_DATA 0x00770005
20 #define SCLP_CMD_WRITE_EVENT_DATA 0x00760005
21 #define SCLP_CMD_WRITE_EVENT_MASK 0x00780005
24 #define SCLP_RC_NORMAL_READ_COMPLETION 0x0010
25 #define SCLP_RC_NORMAL_COMPLETION 0x0020
26 #define SCLP_RC_INVALID_SCLP_COMMAND 0x01f0
[all …]
/qemu/tests/qtest/libqos/
H A Dsdhci-cmd.h20 #define SDHC_BLKSIZE 0x04
21 #define SDHC_BLKCNT 0x06
22 #define SDHC_ARGUMENT 0x08
23 #define SDHC_TRNMOD 0x0C
24 #define SDHC_CMDREG 0x0E
25 #define SDHC_RSPREG0 0x10
26 #define SDHC_BDATA 0x20
27 #define SDHC_PRNSTS 0x24
28 #define SDHC_BLKGAP 0x2A
29 #define SDHC_CLKCON 0x2C
[all …]
/qemu/include/block/
H A Draw-aio.h24 #define QEMU_AIO_READ 0x0001
25 #define QEMU_AIO_WRITE 0x0002
26 #define QEMU_AIO_IOCTL 0x0004
27 #define QEMU_AIO_FLUSH 0x0008
28 #define QEMU_AIO_DISCARD 0x0010
29 #define QEMU_AIO_WRITE_ZEROES 0x0020
30 #define QEMU_AIO_COPY_RANGE 0x0040
31 #define QEMU_AIO_TRUNCATE 0x0080
32 #define QEMU_AIO_ZONE_REPORT 0x0100
33 #define QEMU_AIO_ZONE_MGMT 0x0200
[all …]
/qemu/linux-user/mips/
H A Dsockbits.h17 #define TARGET_SOL_SOCKET 0xffff
19 #define TARGET_SO_DEBUG 0x0001 /* Record debugging information. */
20 #define TARGET_SO_REUSEADDR 0x0004 /* Allow reuse of local addresses. */
21 #define TARGET_SO_KEEPALIVE 0x0008 /* Keep connections alive and send
23 #define TARGET_SO_DONTROUTE 0x0010 /* Don't do local routing. */
24 #define TARGET_SO_BROADCAST 0x0020 /* Allow transmission of
26 #define TARGET_SO_LINGER 0x0080 /* Block on close of a reliable
29 #define TARGET_SO_OOBINLINE 0x0100 /* Receive out-of-band data in-band.
31 #define TARGET_SO_REUSEPORT 0x0200
33 #define TARGET_SO_TYPE 0x1008 /* Compatible name for SO_STYLE. */
[all …]
/qemu/bsd-user/netbsd/
H A Dtarget_os_signal.h44 #define TARGET_SIG_DFL ((void (*)(int))0)
48 #define TARGET_SA_ONSTACK 0x0001 /* take signal on signal stack */
49 #define TARGET_SA_RESTART 0x0002 /* restart system on signal return */
50 #define TARGET_SA_RESETHAND 0x0004 /* reset to SIG_DFL when taking signal */
51 #define TARGET_SA_NODEFER 0x0010 /* don't mask the signal we're delivering */
52 #define TARGET_SA_NOCLDWAIT 0x0020 /* don't create zombies (assign to pid 1) */
53 #define TARGET_SA_USERTRAMP 0x0100 /* do not bounce off kernel's sigtramp */
54 #define TARGET_SA_NOCLDSTOP 0x0008 /* do not generate SIGCHLD on child stop */
55 #define TARGET_SA_SIGINFO 0x0040 /* generate siginfo_t */
66 #define TARGET_SS_ONSTACK 0x0001 /* take signals on alternate stack */
[all …]
/qemu/bsd-user/openbsd/
H A Dtarget_os_signal.h44 #define TARGET_SIG_DFL ((void (*)(int))0)
48 #define TARGET_SA_ONSTACK 0x0001 /* take signal on signal stack */
49 #define TARGET_SA_RESTART 0x0002 /* restart system on signal return */
50 #define TARGET_SA_RESETHAND 0x0004 /* reset to SIG_DFL when taking signal */
51 #define TARGET_SA_NODEFER 0x0010 /* don't mask the signal we're delivering */
52 #define TARGET_SA_NOCLDWAIT 0x0020 /* don't create zombies (assign to pid 1) */
53 #define TARGET_SA_USERTRAMP 0x0100 /* do not bounce off kernel's sigtramp */
54 #define TARGET_SA_NOCLDSTOP 0x0008 /* do not generate SIGCHLD on child stop */
55 #define TARGET_SA_SIGINFO 0x0040 /* generate siginfo_t */
66 #define TARGET_SS_ONSTACK 0x0001 /* take signals on alternate stack */
[all …]
/qemu/target/hexagon/
H A Dcpu.h45 #define MMU_USER_IDX 0
61 #define EXEC_STATUS_OK 0x0000
62 #define EXEC_STATUS_STOP 0x0002
63 #define EXEC_STATUS_REPLAY 0x0010
64 #define EXEC_STATUS_LOCKED 0x0020
65 #define EXEC_STATUS_EXCEPTION 0x0100
134 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
/qemu/bsd-user/freebsd/
H A Dtarget_os_signal.h53 #define TARGET_SIG_DFL ((abi_long)0) /* default signal handling */
57 #define TARGET_SA_ONSTACK 0x0001 /* take signal on signal stack */
58 #define TARGET_SA_RESTART 0x0002 /* restart system on signal return */
59 #define TARGET_SA_RESETHAND 0x0004 /* reset to SIG_DFL when taking signal */
60 #define TARGET_SA_NODEFER 0x0010 /* don't mask the signal we're delivering */
61 #define TARGET_SA_NOCLDWAIT 0x0020 /* don't create zombies (assign to pid 1) */
62 #define TARGET_SA_USERTRAMP 0x0100 /* do not bounce off kernel's sigtramp */
63 #define TARGET_SA_NOCLDSTOP 0x0008 /* do not generate SIGCHLD on child stop */
64 #define TARGET_SA_SIGINFO 0x0040 /* generate siginfo_t */
78 #define TARGET_SS_ONSTACK 0x0001 /* take signals on alternate stack */
[all …]
/qemu/hw/dma/
H A Drc4030.c52 #define DMA_FLAG_ENABLE 0x0001
53 #define DMA_FLAG_MEM_TO_DEV 0x0002
54 #define DMA_FLAG_TC_INTR 0x0100
55 #define DMA_FLAG_MEM_INTR 0x0200
56 #define DMA_FLAG_ADDR_INTR 0x0400
67 uint32_t config; /* 0x0000: RC4030 config register */
68 uint32_t revision; /* 0x0008: RC4030 Revision register */
69 uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
73 uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
74 uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
[all …]
/qemu/hw/rtc/
H A Dallwinner-rtc.c40 REG_GP0, /* General Purpose Register 0 */
77 [0x0000] = REG_LOSC,
78 [0x0004] = REG_YYMMDD,
79 [0x0008] = REG_HHMMSS,
80 [0x000C] = REG_ALARM1_DDHHMMSS,
81 [0x0010] = REG_ALARM1_WKHHMMSS,
82 [0x0014] = REG_ALARM1_EN,
83 [0x0018] = REG_ALARM1_IRQ_EN,
84 [0x001C] = REG_ALARM1_IRQ_STA,
85 [0x0020] = REG_GP0,
[all …]
/qemu/hw/net/
H A Ddp8393x.c38 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
41 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
42 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
44 #define SONIC_CR 0x00
45 #define SONIC_DCR 0x01
46 #define SONIC_RCR 0x02
47 #define SONIC_TCR 0x03
48 #define SONIC_IMR 0x04
49 #define SONIC_ISR 0x05
50 #define SONIC_UTDA 0x06
[all …]
/qemu/hw/scsi/
H A Dmfi.h44 #define MFI_IMSG0 0x10 /* Inbound message 0 */
45 #define MFI_IMSG1 0x14 /* Inbound message 1 */
46 #define MFI_OMSG0 0x18 /* Outbound message 0 */
47 #define MFI_OMSG1 0x1c /* Outbound message 1 */
48 #define MFI_IDB 0x20 /* Inbound doorbell */
49 #define MFI_ISTS 0x24 /* Inbound interrupt status */
50 #define MFI_IMSK 0x28 /* Inbound interrupt mask */
51 #define MFI_ODB 0x2c /* Outbound doorbell */
52 #define MFI_OSTS 0x30 /* Outbound interrupt status */
53 #define MFI_OMSK 0x34 /* Outbound interrupt mask */
[all …]
/qemu/include/hw/intc/
H A Dmips_gic.h24 #define GIC_BASE_ADDR 0x1bdc0000ULL
29 #define GIC_POL_NEG 0
31 #define GIC_TRIG_LEVEL 0
36 #define SHARED_SECTION_OFS 0x0000
37 #define SHARED_SECTION_SIZE 0x8000
38 #define VP_LOCAL_SECTION_OFS 0x8000
39 #define VP_LOCAL_SECTION_SIZE 0x4000
40 #define VP_OTHER_SECTION_OFS 0xc000
41 #define VP_OTHER_SECTION_SIZE 0x4000
42 #define USM_VISIBLE_SECTION_OFS 0x10000
[all …]

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