hw/rtc/allwinner-rtc.c

40     REG_GP0,             /* General Purpose Register 0 */
77     [0x0000] = REG_LOSC,
78     [0x0004] = REG_YYMMDD,
79     [0x0008] = REG_HHMMSS,
80     [0x000C] = REG_ALARM1_DDHHMMSS,
81     [0x0010] = REG_ALARM1_WKHHMMSS,
82     [0x0014] = REG_ALARM1_EN,
83     [0x0018] = REG_ALARM1_IRQ_EN,
84     [0x001C] = REG_ALARM1_IRQ_STA,
85     [0x0020] = REG_GP0,
86     [0x0024] = REG_GP1,
87     [0x0028] = REG_GP2,
88     [0x002C] = REG_GP3,
89     [0x003C] = REG_CPUCFG,
94     [0x0000] = REG_LOSC,
95     [0x0004] = REG_LOSC_AUTOSTA,
96     [0x0008] = REG_INT_OSC_PRE,
97     [0x0010] = REG_YYMMDD,
98     [0x0014] = REG_HHMMSS,
99     [0x0020] = REG_ALARM0_COUNTER,
100     [0x0024] = REG_ALARM0_CUR_VLU,
101     [0x0028] = REG_ALARM0_ENABLE,
102     [0x002C] = REG_ALARM0_IRQ_EN,
103     [0x0030] = REG_ALARM0_IRQ_STA,
104     [0x0040] = REG_ALARM1_WKHHMMSS,
105     [0x0044] = REG_ALARM1_EN,
106     [0x0048] = REG_ALARM1_IRQ_EN,
107     [0x004C] = REG_ALARM1_IRQ_STA,
108     [0x0050] = REG_ALARM_CONFIG,
109     [0x0060] = REG_LOSC_OUT_GATING,
110     [0x0100] = REG_GP0,
111     [0x0104] = REG_GP1,
112     [0x0108] = REG_GP2,
113     [0x010C] = REG_GP3,
114     [0x0110] = REG_GP4,
115     [0x0114] = REG_GP5,
116     [0x0118] = REG_GP6,
117     [0x011C] = REG_GP7,
118     [0x0170] = REG_RTC_DBG,
119     [0x0180] = REG_GPL_HOLD_OUT,
120     [0x0190] = REG_VDD_RTC,
121     [0x01F0] = REG_IC_CHARA,
175     uint64_t val = 0;  in allwinner_rtc_read()
178         qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",  in allwinner_rtc_read()
180         return 0;  in allwinner_rtc_read()
184             qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",  in allwinner_rtc_read()
186         return 0;  in allwinner_rtc_read()
196     case REG_GP0:        /* General Purpose Register 0 */  in allwinner_rtc_read()
204             qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",  in allwinner_rtc_read()
222         qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",  in allwinner_rtc_write()
228             qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",  in allwinner_rtc_write()
244     case REG_GP0:        /* General Purpose Register 0 */  in allwinner_rtc_write()
252             qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",  in allwinner_rtc_write()
276     memset(s->regs, 0, sizeof(s->regs));  in allwinner_rtc_reset()
279     qemu_get_timedate(&now, 0);  in allwinner_rtc_reset()
315     DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0),