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/qemu/target/openrisc/
H A Ddisas.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * You should have received a copy of the GNU General Public License
21 #include "disas/dis-asm.h"
27 /* Include the auto-generated decoder. */
28 #include "decode-insns.c.inc"
31 (info->fprintf_func(info->stream, "%-9s " format, \
40 status = info->read_memory_func(addr, buffer, 4, info); in print_insn_or1k()
42 info->memory_error_func(status, addr, info); in print_insn_or1k()
43 return -1; in print_insn_or1k()
54 static bool trans_l_##opcode(disassemble_info *info, arg_l_##opcode *a) \
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H A Dtranslate.c4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * You should have received a copy of the GNU Lesser General Public
23 #include "accel/tcg/cpu-mmu-index.h"
24 #include "tcg/tcg-op.h"
27 #include "qemu/qemu-print.h"
29 #include "exec/translation-block.h"
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
37 #include "exec/helper-info.c.inc"
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H A Dinsns.decode13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 # You should have received a copy of the GNU Lesser General Public
20 &dab d a b
21 &da d a
22 &ab a b
23 &dal d a l
24 &ai a i
25 &dab_pair d a b dp ap bp
26 &ab_pair a b ap bp
27 &da_pair d a dp ap
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/qemu/target/riscv/insn_trans/
H A Dtrans_rvd.c.inc2 * RISC-V translation routines for the RV64D Standard Extension.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
22 if (!ctx->cfg_ptr->ext_zdinx) { \
28 if (ctx->cfg_ptr->ext_zdinx && (get_xl(ctx) == MXL_RV32) && \
35 if (!ctx->cfg_ptr->ext_zcd) { \
42 static bool trans_fld(DisasContext *ctx, arg_fld *a)
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H A Dtrans_rvzfh.c.inc2 * RISC-V translation routines for the RV64Zfh Standard Extension.
4 * Copyright (c) 2020 Chih-Min Chao, chihmin.chao@sifive.com
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
20 if (!ctx->cfg_ptr->ext_zfh) { \
26 if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \
32 if (!ctx->cfg_ptr->ext_zfhmin && !ctx->cfg_ptr->ext_zfbfmin) { \
38 if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \
43 static bool trans_flh(DisasContext *ctx, arg_flh *a)
52 t0 = get_gpr(ctx, a->rs1, EXT_NONE);
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H A Dtrans_rvf.c.inc2 * RISC-V translation routines for the RV64F Standard Extension.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
22 if (ctx->mstatus_fs == EXT_STATUS_DISABLED) { \
23 ctx->virt_inst_excp = ctx->virt_enabled && ctx->cfg_ptr->ext_zfinx; \
29 if (!ctx->cfg_ptr->ext_zfinx) { \
35 if (!ctx->cfg_ptr->ext_zcf) { \
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H A Dtrans_rvi.c.inc2 * RISC-V translation routines for the RVXI Base Integer Instruction Set.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
21 static bool trans_illegal(DisasContext *ctx, arg_empty *a)
27 static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
30 return trans_illegal(ctx, a);
33 static bool trans_lui(DisasContext *ctx, arg_lui *a)
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H A Dtrans_rvvk.c.inc2 * RISC-V translation routines for the vector crypto extension.
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
25 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
27 if (CHECK(s, a)) { \
28 return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \
34 static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a)
36 return opivv_check(s, a) &&
37 s->cfg_ptr->ext_zvbc == true &&
38 s->sew == MO_64;
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H A Dtrans_rvzfa.c.inc2 * RISC-V translation routines for the Zfa Standard Extension.
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
20 if (!ctx->cfg_ptr->ext_zfa) { \
26 if (!ctx->cfg_ptr->ext_zfh) { \
31 static bool trans_fli_s(DisasContext *ctx, arg_fli_s *a)
37 /* Values below are NaN-boxed to avoid a gen_nanbox_s(). */
39 0xffffffffbf800000, /* -1.0 */
41 0xffffffff37800000, /* 1.0 * 2^-16 */
42 0xffffffff38000000, /* 1.0 * 2^-15 */
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/qemu/target/rx/
H A Ddisas.c12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
20 #include "disas/dis-asm.h"
36 uint32_t addr = ctx->addr; in decode_load_bytes()
38 g_assert(ctx->len == i); in decode_load_bytes()
39 g_assert(n <= ARRAY_SIZE(ctx->bytes)); in decode_load_bytes()
42 ctx->dis->read_memory_func(addr++, &ctx->bytes[i - 1], 1, ctx->dis); in decode_load_bytes()
43 insn |= ctx->bytes[i - 1] << (32 - i * 8); in decode_load_bytes()
45 ctx->addr = addr; in decode_load_bytes()
46 ctx->len = n; in decode_load_bytes()
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H A Dtranslate.c12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
21 #include "qemu/qemu-print.h"
23 #include "tcg/tcg-op.h"
24 #include "exec/helper-proto.h"
25 #include "exec/helper-gen.h"
27 #include "exec/translation-block.h"
31 #include "exec/helper-info.c.inc"
60 /* Target-specific values for dc->base.is_jmp. */
80 uint8_t b = translator_ldub(ctx->env, &ctx->base, ctx->base.pc_next++); in decode_load_bytes()
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/qemu/target/avr/
H A Ddisas.c4 * Copyright (c) 2019-2020 Richard Henderson <rth@twiddle.net>
5 * Copyright (c) 2019-2020 Michael Rolnik <mrolnik@gmail.com>
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * You should have received a copy of the GNU General Public License
52 ctx->next_word_used = true; in next_word()
53 return ctx->next_word; in next_word()
61 /* Include the auto-generated decoder. */
63 #include "decode-insn.c.inc"
66 (pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \
77 status = info->read_memory_func(addr, buffer, 2, info); in avr_print_insn()
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/qemu/target/ppc/translate/
H A Dfixedpoint-impl.c.inc2 * Power ISA decode for Fixed-Point Facility instructions
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
21 * Fixed-Point Load/Store Instructions
36 mop ^= ctx->default_tcg_memop_mask;
38 tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
40 tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
48 static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
51 return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
54 static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
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/qemu/fpu/
H A Dsoftfloat.c4 * The code in this source file is derived from release 2a of the SoftFloat
5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
9 * the SoftFloat-2a license
11 * GPL-v2-or-later
14 * taken to be licensed under the Softfloat-2a license unless specifically
20 This C source file is part of the SoftFloat IEC/IEEE Floating-point
21 Arithmetic Package, Release 2a.
26 National Science Foundation under grant MIP-9311980. The original version
27 of this code was written as part of a project to build a fixed-point vector
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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/qemu/target/mips/tcg/
H A Dtx79_translate.c2 * Toshiba TX79-specific instructions translation routines
5 * Copyright (c) 2021 Philippe Mathieu-Daudé
7 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "tcg/tcg-op-gvec.h"
14 /* Include the auto-generated decoder. */
15 #include "decode-tx79.c.inc"
18 * Overview of the TX79-specific instruction set
21 * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
22 * are only used by the specific quadword (128-bit) LQ/SQ load/store
24 * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
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H A Docteon_translate.c2 * Octeon-specific instructions translation routines
6 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "tcg/tcg-op-gvec.h"
13 /* Include the auto-generated decoder. */
14 #include "decode-octeon.c.inc"
16 static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) in trans_BBIT() argument
20 if (ctx->hflags & MIPS_HFLAG_BMASK) { in trans_BBIT()
22 ctx->base.pc_next); in trans_BBIT()
29 gen_load_gpr(t0, a->rs); in trans_BBIT()
31 p = tcg_constant_tl(1ULL << a->p); in trans_BBIT()
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/qemu/target/arm/tcg/
H A Dtranslate-a64.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
22 #include "translate-a64.h"
74 #include "decode-sme-fa64.c.inc"
75 #include "decode-a64.c.inc"
97 * have a "unprivileged load/store" variant. Those insns access
112 ARMMMUIdx useridx = s->mmu_idx; in get_a64_user_mem_index()
114 if (unpriv && s->unpriv) { in get_a64_user_mem_index()
116 * We have pre-computed the condition for AccType_UNPRIV. in get_a64_user_mem_index()
117 * Therefore we should never get here with a mmu_idx for in get_a64_user_mem_index()
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H A Dtranslate-neon.c5 * Copyright (c) 2005-2007 CodeSourcery
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * You should have received a copy of the GNU Lesser General Public
25 #include "translate-a32.h"
28 #include "decode-neon-dp.c.inc"
29 #include "decode-neon-ls.c.inc"
30 #include "decode-neon-shared.c.inc"
124 /* UNDEF accesses to D16-D31 if they don't exist. */ in do_neon_ddda()
131 * Q will be 0b111 for all Q-reg instructions, otherwise in do_neon_ddda()
132 * when we have mixed Q- and D-reg inputs. in do_neon_ddda()
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H A Dtranslate-sve.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
22 #include "translate-a64.h"
43 * Returns -1 for unallocated encoding; diagnose later.
48 return 31 - clz32(x); in tszimm_esz()
54 * We won't use the tszimm_shr() value if tszimm_esz() returns -1 (the in tszimm_shr()
62 return (16 << esz) - x; in tszimm_shr()
73 return x - (8 << esz); in tszimm_shl()
87 /* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype)
100 #include "decode-sve.c.inc"
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H A Dtranslate-mve.c2 * ARM translation: M-profile MVE instructions
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
22 #include "translate-a32.h"
30 #include "decode-mve.c.inc"
50 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
67 * with no predication or partial-execution, and so we can safely in mve_no_predication()
70 return s->eci == 0 && s->mve_no_pred; in mve_no_predication()
85 * This is a beatwise insn: check that ECI is valid (not a in mve_eci_check()
89 s->eci_handled = true; in mve_eci_check()
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H A Dtranslate-vfp.c5 * Copyright (c) 2005-2007 CodeSourcery
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * You should have received a copy of the GNU Lesser General Public
25 #include "translate-a32.h"
28 #include "decode-vfp.c.inc"
29 #include "decode-vfp-uncond.c.inc"
91 * Return the offset of a 16-bit half of the specified VFP single-precision
111 * Generate code for M-profile lazy FP state preservation if needed;
116 if (s->v7m_lspact) { in gen_preserve_fp_state()
122 if (translator_io_start(&s->base)) { in gen_preserve_fp_state()
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/qemu/include/fpu/
H A Dsoftfloat.h4 * The code in this source file is derived from release 2a of the SoftFloat
5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
9 * the SoftFloat-2a license
11 * GPL-v2-or-later
14 * taken to be licensed under the Softfloat-2a license unless specifically
20 This C header file is part of the SoftFloat IEC/IEEE Floating-point
21 Arithmetic Package, Release 2a.
26 National Science Foundation under grant MIP-9311980. The original version
27 of this code was written as part of a project to build a fixed-point vector
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
[all …]
/qemu/tests/qemu-iotests/
H A D059.out5 qemu-io: can't open device TEST_DIR/t.vmdk: Invalid granularity, image may be corrupt
9 qemu-io: can't open device TEST_DIR/t.vmdk: L2 table size too big
13 qemu-io: can't open device TEST_DIR/t.vmdk: L1 size too big
23 qemu-img: TEST_DIR/t.IMGFMT: Flat image can't enable zeroed grain
37 filename: TEST_DIR/t-f001.IMGFMT
41 filename: TEST_DIR/t-f002.IMGFMT
45 filename: TEST_DIR/t-f003.IMGFMT
49 filename: TEST_DIR/t-f004.IMGFMT
53 filename: TEST_DIR/t-f005.IMGFMT
57 filename: TEST_DIR/t-f006.IMGFMT
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/qemu/target/hppa/
H A Dtranslate.c13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
22 #include "qemu/host-utils.h"
23 #include "exec/page-protection.h"
24 #include "tcg/tcg-op.h"
25 #include "tcg/tcg-op-gvec.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translation-block.h"
34 #include "exec/helper-info.c.inc"
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/qemu/docs/
H A Dglossary.rst3 --------
5 --------
11 -----------
13 A specific API used to accelerate execution of guest instructions. It can be
14 hardware-based, through a virtualization API provided by the host OS (kvm, hvf,
15 whpx, ...), or software-based (tcg). See this description of `supported
19 -----
24 -----
26 Block drivers are the available `disk formats and front-ends
27 <block-drivers>` available, and block devices `(see Block device section on
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