2  * Octeon-specific instructions translation routines
6  * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "tcg/tcg-op-gvec.h"
13 /* Include the auto-generated decoder.  */
14 #include "decode-octeon.c.inc"
16 static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)  in trans_BBIT()  argument
20     if (ctx->hflags & MIPS_HFLAG_BMASK) {  in trans_BBIT()
22                   ctx->base.pc_next);  in trans_BBIT()
29     gen_load_gpr(t0, a->rs);  in trans_BBIT()
31     p = tcg_constant_tl(1ULL << a->p);  in trans_BBIT()
32     if (a->set) {  in trans_BBIT()
38     ctx->hflags |= MIPS_HFLAG_BC;  in trans_BBIT()
39     ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4;  in trans_BBIT()
40     ctx->hflags |= MIPS_HFLAG_BDS32;  in trans_BBIT()
44 static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)  in trans_BADDU()  argument
48     if (a->rt == 0) {  in trans_BADDU()
55     gen_load_gpr(t0, a->rs);  in trans_BADDU()
56     gen_load_gpr(t1, a->rt);  in trans_BADDU()
59     tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);  in trans_BADDU()
63 static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)  in trans_DMUL()  argument
67     if (a->rt == 0) {  in trans_DMUL()
74     gen_load_gpr(t0, a->rs);  in trans_DMUL()
75     gen_load_gpr(t1, a->rt);  in trans_DMUL()
77     tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);  in trans_DMUL()
81 static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)  in trans_EXTS()  argument
85     if (a->rt == 0) {  in trans_EXTS()
91     gen_load_gpr(t0, a->rs);  in trans_EXTS()
92     tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1);  in trans_EXTS()
93     gen_store_gpr(t0, a->rt);  in trans_EXTS()
97 static bool trans_CINS(DisasContext *ctx, arg_CINS *a)  in trans_CINS()  argument
101     if (a->rt == 0) {  in trans_CINS()
107     gen_load_gpr(t0, a->rs);  in trans_CINS()
108     tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1);  in trans_CINS()
109     gen_store_gpr(t0, a->rt);  in trans_CINS()
113 static bool trans_POP(DisasContext *ctx, arg_POP *a)  in trans_POP()  argument
117     if (a->rd == 0) {  in trans_POP()
123     gen_load_gpr(t0, a->rs);  in trans_POP()
124     if (!a->dw) {  in trans_POP()
128     gen_store_gpr(t0, a->rd);  in trans_POP()
132 static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)  in trans_SEQNE()  argument
136     if (a->rd == 0) {  in trans_SEQNE()
144     gen_load_gpr(t0, a->rs);  in trans_SEQNE()
145     gen_load_gpr(t1, a->rt);  in trans_SEQNE()
147     if (a->ne) {  in trans_SEQNE()
148         tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);  in trans_SEQNE()
150         tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);  in trans_SEQNE()
155 static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)  in trans_SEQNEI()  argument
159     if (a->rt == 0) {  in trans_SEQNEI()
166     gen_load_gpr(t0, a->rs);  in trans_SEQNEI()
168     /* Sign-extend to 64 bit value */  in trans_SEQNEI()
169     target_ulong imm = a->imm;  in trans_SEQNEI()
170     if (a->ne) {  in trans_SEQNEI()
171         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);  in trans_SEQNEI()
173         tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);  in trans_SEQNEI()