Lines Matching +full:- +full:a +full:-
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * You should have received a copy of the GNU Lesser General Public
22 #include "qemu/host-utils.h"
23 #include "exec/page-protection.h"
24 #include "tcg/tcg-op.h"
25 #include "tcg/tcg-op-gvec.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translation-block.h"
34 #include "exec/helper-info.c.inc"
100 #define UNALIGN(C) (C)->unalign
104 #define MMU_DISABLED(C) MMU_IDX_MMU_DISABLED((C)->mmu_idx)
110 /* Keep unimplemented bits disabled -- see cpu_hppa_put_psw. */ in expand_sm_imm()
111 if (ctx->is_pa20) { in expand_sm_imm()
128 /* Convert the M:A bits within a memory insn to the tri-state value
132 return val & 2 ? (val & 1 ? -1 : 1) : 0; in ma_to_m()
135 /* Convert the sign of the displacement to a pre or post-modify. */
138 return val ? 1 : -1; in pos_to_m()
143 return val ? -1 : 1; in neg_to_m()
161 * Officially, 32 * x + 32 - y. in assemble_6()
163 * Since -y = ~y + 1, in 5 bits 32 - y => y ^ 31 + 1, in assemble_6()
178 int i = (-(val & 1) << 13) | (im10a << 3); in expand_11a()
180 if (ctx->tb_flags & PSW_W) { in expand_11a()
195 int i = (-(val & 1) << 13) | (im11a << 2); in expand_12a()
197 if (ctx->tb_flags & PSW_W) { in expand_12a()
211 int i = (-(val & 1) << 13) | extract32(val, 1, 13); in expand_16()
213 if (ctx->tb_flags & PSW_W) { in expand_16()
222 return ctx->tb_flags & PSW_W ? 0 : sp; in sp0_if_wide()
237 return ctx->is_pa20 & val; in pa20_d()
240 /* Include the auto-generated decoder. */
241 #include "decode-insns.c.inc"
243 /* We are not using a goto_tb (for whatever reason), but have updated
247 /* We are exiting the TB, but have neither emitted a goto_tb, nor
295 /* SR[4-7] are not global registers so that we can index them. */ in hppa_translate_init()
319 *v->var = tcg_global_mem_new(tcg_env, v->ofs, v->name); in hppa_translate_init()
335 assert(!ctx->insn_start_updated); in set_insn_breg()
336 ctx->insn_start_updated = true; in set_insn_breg()
337 tcg_set_insn_start_param(ctx->base.insn_start, 2, breg); in set_insn_breg()
398 return ctx->zero; in load_gpr()
406 if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) { in dest_gpr()
415 if (ctx->null_cond.c != TCG_COND_NEVER) { in save_or_nullify()
416 tcg_gen_movcond_i64(ctx->null_cond.c, dest, ctx->null_cond.a0, in save_or_nullify()
417 ctx->null_cond.a1, dest, t); in save_or_nullify()
511 } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { in load_spr()
520 * Write a value to psw_xb, bearing in mind the known value.
526 if (ctx->psw_xb != xb) { in store_psw_xb()
531 /* Write a value to psw_xb, and update the known value. */
535 ctx->psw_xb = xb; in set_psw_xb()
539 Use this when the insn is too complex for a conditional move. */
542 if (ctx->null_cond.c != TCG_COND_NEVER) { in nullify_over()
544 assert(ctx->null_cond.c != TCG_COND_ALWAYS); in nullify_over()
546 ctx->null_lab = gen_new_label(); in nullify_over()
548 /* If we're using PSW[N], copy it to a temp because... */ in nullify_over()
549 if (ctx->null_cond.a0 == cpu_psw_n) { in nullify_over()
550 ctx->null_cond.a0 = tcg_temp_new_i64(); in nullify_over()
551 tcg_gen_mov_i64(ctx->null_cond.a0, cpu_psw_n); in nullify_over()
556 if (ctx->psw_n_nonzero) { in nullify_over()
557 ctx->psw_n_nonzero = false; in nullify_over()
561 tcg_gen_brcond_i64(ctx->null_cond.c, ctx->null_cond.a0, in nullify_over()
562 ctx->null_cond.a1, ctx->null_lab); in nullify_over()
563 ctx->null_cond = cond_make_f(); in nullify_over()
570 if (ctx->null_cond.c == TCG_COND_NEVER) { in nullify_save()
571 if (ctx->psw_n_nonzero) { in nullify_save()
576 if (ctx->null_cond.a0 != cpu_psw_n) { in nullify_save()
577 tcg_gen_setcond_i64(ctx->null_cond.c, cpu_psw_n, in nullify_save()
578 ctx->null_cond.a0, ctx->null_cond.a1); in nullify_save()
579 ctx->psw_n_nonzero = true; in nullify_save()
581 ctx->null_cond = cond_make_f(); in nullify_save()
584 /* Set a PSW[N] to X. The intention is that this is used immediately
585 before a goto_tb/exit_tb, so that there is no fallthru path to other
589 if (ctx->psw_n_nonzero || x) { in nullify_set()
596 it may be tail-called from a translate function. */
599 TCGLabel *null_lab = ctx->null_lab; in nullify_end()
600 DisasJumpType status = ctx->base.is_jmp; in nullify_end()
606 assert(!ctx->psw_b_next); in nullify_end()
610 applied to it without a branch, so the (new) setting of in nullify_end()
614 ctx->null_lab = NULL; in nullify_end()
616 if (likely(ctx->null_cond.c == TCG_COND_NEVER)) { in nullify_end()
627 ctx->null_cond = cond_make_n(); in nullify_end()
630 ctx->base.is_jmp = DISAS_NEXT; in nullify_end()
637 return e->base || e->space; in iaqe_variable()
643 .space = e->space, in iaqe_incr()
644 .base = e->base, in iaqe_incr()
645 .disp = e->disp + disp, in iaqe_incr()
652 .space = ctx->iaq_b.space, in iaqe_branchi()
653 .disp = ctx->iaq_f.disp + 8 + disp, in iaqe_branchi()
660 .space = ctx->iaq_b.space, in iaqe_next_absv()
668 tcg_gen_addi_i64(dest, src->base ? : cpu_iaoq_f, src->disp); in copy_iaoq_entry()
689 if (f->base != cpu_iaoq_b) { in install_iaq_entries()
692 } else if (f->base == b->base) { in install_iaq_entries()
694 tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, b->disp - f->disp); in install_iaq_entries()
702 if (f->space) { in install_iaq_entries()
703 tcg_gen_mov_i64(cpu_iasq_f, f->space); in install_iaq_entries()
705 if (b->space || f->space) { in install_iaq_entries()
706 tcg_gen_mov_i64(cpu_iasq_b, b->space ? : f->space); in install_iaq_entries()
712 tcg_debug_assert(ctx->null_cond.c == TCG_COND_NEVER); in install_link()
716 DisasIAQE next = iaqe_incr(&ctx->iaq_b, 4); in install_link()
732 install_iaq_entries(ctx, &ctx->iaq_f, &ctx->iaq_b); in gen_excp()
735 ctx->base.is_jmp = DISAS_NORETURN; in gen_excp()
743 e->next = ctx->delay_excp_list; in delay_excp()
744 ctx->delay_excp_list = e; in delay_excp()
746 e->lab = gen_new_label(); in delay_excp()
747 e->insn = ctx->insn; in delay_excp()
748 e->set_iir = true; in delay_excp()
749 e->set_n = ctx->psw_n_nonzero ? 0 : -1; in delay_excp()
750 e->excp = excp; in delay_excp()
751 e->iaq_f = ctx->iaq_f; in delay_excp()
752 e->iaq_b = ctx->iaq_b; in delay_excp()
759 if (ctx->null_cond.c == TCG_COND_NEVER) { in gen_excp_iir()
760 tcg_gen_st_i64(tcg_constant_i64(ctx->insn), in gen_excp_iir()
765 tcg_gen_brcond_i64(tcg_invert_cond(ctx->null_cond.c), in gen_excp_iir()
766 ctx->null_cond.a0, ctx->null_cond.a1, e->lab); in gen_excp_iir()
767 ctx->null_cond = cond_make_f(); in gen_excp_iir()
783 if (ctx->privilege != 0) { \
794 translator_use_goto_tb(&ctx->base, ctx->iaoq_first + f->disp)); in use_goto_tb()
798 and we're not attempting to set a breakpoint on it, then we can
800 executing a TB that merely branches to the next TB. */
803 return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) in use_nullify_skip()
804 && !iaqe_variable(&ctx->iaq_b) in use_nullify_skip()
805 && (((ctx->iaoq_first + ctx->iaq_b.disp) ^ ctx->iaoq_first) in use_nullify_skip()
815 tcg_gen_exit_tb(ctx->base.tb, which); in gen_goto_tb()
832 * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
845 /* 64-bit condition. */ in do_cond()
851 /* 32-bit condition. */ in do_cond()
883 ctx->zero, res); in do_cond()
891 tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res); in do_cond()
1023 0-2 are the same as logicals (nv,<,<=), while 3 is OD. in do_sed_cond()
1024 4-7 are the reverse of 0-3. */ in do_sed_cond()
1122 tcg_gen_extract_i64(tmp, tmp, sign_bit - shift, shift); in do_add_sv()
1123 tcg_gen_movcond_i64(TCG_COND_NE, sv, tmp, ctx->zero, in do_add_sv()
1124 tcg_constant_i64(-1), sv); in do_add_sv()
1138 tcg_gen_extract_i64(tmp, in1, (d ? 63 : 31) - shift, shift); in do_add_uv()
1162 switch (cond->c) { in gen_tc()
1170 tcg_gen_brcond_i64(cond->c, cond->a0, cond->a1, e->lab); in gen_tc()
1171 /* In the non-trap path, the condition is known false. */ in gen_tc()
1182 tcg_gen_brcond_i64(cond.c, cond.a0, cond.a1, e->lab); in gen_tsv()
1184 /* In the non-trap path, V is known zero. */ in gen_tsv()
1214 tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero); in do_add()
1254 ctx->null_cond = cond; in do_add()
1257 static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a, in do_add_reg() argument
1262 if (unlikely(is_tc && a->cf == 1)) { in do_add_reg()
1266 if (a->cf) { in do_add_reg()
1269 tcg_r1 = load_gpr(ctx, a->r1); in do_add_reg()
1270 tcg_r2 = load_gpr(ctx, a->r2); in do_add_reg()
1271 do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, in do_add_reg()
1272 is_tsv, is_tc, is_c, a->cf, a->d); in do_add_reg()
1276 static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, in do_add_imm() argument
1281 if (unlikely(is_tc && a->cf == 1)) { in do_add_imm()
1285 if (a->cf) { in do_add_imm()
1288 tcg_im = tcg_constant_i64(a->i); in do_add_imm()
1289 tcg_r2 = load_gpr(ctx, a->r); in do_add_imm()
1290 /* All ADDI conditions are 32-bit. */ in do_add_imm()
1291 do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf, false); in do_add_imm()
1319 tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero); in do_sub()
1351 ctx->null_cond = cond; in do_sub()
1354 static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf_d *a, in do_sub_reg() argument
1359 if (a->cf) { in do_sub_reg()
1362 tcg_r1 = load_gpr(ctx, a->r1); in do_sub_reg()
1363 tcg_r2 = load_gpr(ctx, a->r2); in do_sub_reg()
1364 do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf, a->d); in do_sub_reg()
1368 static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv) in do_sub_imm() argument
1372 if (a->cf) { in do_sub_imm()
1375 tcg_im = tcg_constant_i64(a->i); in do_sub_imm()
1376 tcg_r2 = load_gpr(ctx, a->r); in do_sub_imm()
1377 /* All SUBI conditions are 32-bit. */ in do_sub_imm()
1378 do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf, false); in do_sub_imm()
1405 ctx->null_cond = cond; in do_cmpclr()
1419 ctx->null_cond = do_log_cond(ctx, cf, d, dest); in do_log()
1422 static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, in do_log_reg() argument
1427 if (a->cf) { in do_log_reg()
1430 tcg_r1 = load_gpr(ctx, a->r1); in do_log_reg()
1431 tcg_r2 = load_gpr(ctx, a->r2); in do_log_reg()
1432 do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn); in do_log_reg()
1444 /* Select which carry-out bits to test. */ in do_unit_addsub()
1446 case 4: /* NDC / SDC -- 4-bit carries */ in do_unit_addsub()
1449 case 5: /* NWC / SWC -- 32-bit carries */ in do_unit_addsub()
1453 cf &= 1; /* undefined -- map to never/always */ in do_unit_addsub()
1456 case 6: /* NBC / SBC -- 8-bit carries */ in do_unit_addsub()
1459 case 7: /* NHC / SHC -- 16-bit carries */ in do_unit_addsub()
1481 tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero); in do_unit_addsub()
1486 tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero); in do_unit_addsub()
1512 ctx->null_cond = cond; in do_unit_addsub()
1517 from the top 2 bits of the base register. There are a few system
1518 instructions that have a 3-bit space specifier, for which SR0 is
1534 if (ctx->tb_flags & TB_FLAG_SR_SAME) { in space_select()
1543 tcg_gen_shri_i64(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); in space_select()
1579 ctx->gva_offset_mask); in form_gva()
1587 /* Emit a memory load. The modify parameter should be
1588 * < 0 for pre-modify,
1589 * > 0 for post-modify,
1600 assert(ctx->null_cond.c == TCG_COND_NEVER); in do_load_32()
1604 tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); in do_load_32()
1618 assert(ctx->null_cond.c == TCG_COND_NEVER); in do_load_64()
1622 tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); in do_load_64()
1636 assert(ctx->null_cond.c == TCG_COND_NEVER); in do_store_32()
1640 tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); in do_store_32()
1654 assert(ctx->null_cond.c == TCG_COND_NEVER); in do_store_64()
1658 tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); in do_store_64()
1704 static bool trans_fldw(DisasContext *ctx, arg_ldst *a) in trans_fldw() argument
1706 return do_floadw(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, in trans_fldw()
1707 a->disp, a->sp, a->m); in trans_fldw()
1729 static bool trans_fldd(DisasContext *ctx, arg_ldst *a) in trans_fldd() argument
1731 return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, in trans_fldd()
1732 a->disp, a->sp, a->m); in trans_fldd()
1758 static bool trans_fstw(DisasContext *ctx, arg_ldst *a) in trans_fstw() argument
1760 return do_fstorew(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, in trans_fstw()
1761 a->disp, a->sp, a->m); in trans_fstw()
1778 static bool trans_fstd(DisasContext *ctx, arg_ldst *a) in trans_fstd() argument
1780 return do_fstored(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, in trans_fstd()
1781 a->disp, a->sp, a->m); in trans_fstd()
1848 TCGv_i32 a, b; in do_fop_weww() local
1851 a = load_frw0_i32(ra); in do_fop_weww()
1854 func(a, tcg_env, a, b); in do_fop_weww()
1856 save_frw_i32(rt, a); in do_fop_weww()
1864 TCGv_i64 a, b; in do_fop_dedd() local
1867 a = load_frd0(ra); in do_fop_dedd()
1870 func(a, tcg_env, a, b); in do_fop_dedd()
1872 save_frd(rt, a); in do_fop_dedd()
1876 /* Emit an unconditional branch to a direct target, which may or may not
1881 ctx->iaq_j = iaqe_branchi(ctx, disp); in do_dbranch()
1883 if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { in do_dbranch()
1889 gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); in do_dbranch()
1890 ctx->base.is_jmp = DISAS_NORETURN; in do_dbranch()
1893 ctx->null_cond.c = TCG_COND_ALWAYS; in do_dbranch()
1895 ctx->iaq_n = &ctx->iaq_j; in do_dbranch()
1896 ctx->psw_b_next = true; in do_dbranch()
1904 gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); in do_dbranch()
1908 gen_goto_tb(ctx, 0, &ctx->iaq_b, &ctx->iaq_j); in do_dbranch()
1914 gen_goto_tb(ctx, 1, &ctx->iaq_b, NULL); in do_dbranch()
1915 ctx->base.is_jmp = DISAS_NORETURN; in do_dbranch()
1920 /* Emit a conditional branch to a direct target. If the branch itself
1927 TCGCond c = cond->c; in do_cbranch()
1930 assert(ctx->null_cond.c == TCG_COND_NEVER); in do_cbranch()
1938 tcg_gen_brcond_i64(c, cond->a0, cond->a1, taken); in do_cbranch()
1945 next = iaqe_incr(&ctx->iaq_b, 4); in do_cbranch()
1948 if (!n && ctx->null_lab) { in do_cbranch()
1949 gen_set_label(ctx->null_lab); in do_cbranch()
1950 ctx->null_lab = NULL; in do_cbranch()
1954 gen_goto_tb(ctx, 0, &ctx->iaq_b, NULL); in do_cbranch()
1970 gen_goto_tb(ctx, 1, &ctx->iaq_b, &next); in do_cbranch()
1974 if (ctx->null_lab) { in do_cbranch()
1975 gen_set_label(ctx->null_lab); in do_cbranch()
1976 ctx->null_lab = NULL; in do_cbranch()
1977 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in do_cbranch()
1979 ctx->base.is_jmp = DISAS_NORETURN; in do_cbranch()
1985 * Emit an unconditional branch to an indirect target, in ctx->iaq_j.
1991 if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { in do_ibranch()
1995 install_iaq_entries(ctx, &ctx->iaq_j, NULL); in do_ibranch()
1997 ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; in do_ibranch()
2000 ctx->null_cond.c = TCG_COND_ALWAYS; in do_ibranch()
2002 ctx->iaq_n = &ctx->iaq_j; in do_ibranch()
2003 ctx->psw_b_next = true; in do_ibranch()
2011 install_iaq_entries(ctx, &ctx->iaq_j, NULL); in do_ibranch()
2015 install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); in do_ibranch()
2021 ctx->base.is_jmp = DISAS_NORETURN; in do_ibranch()
2035 switch (ctx->privilege) { in do_ibranch_priv()
2045 tcg_gen_andi_i64(dest, offset, -4); in do_ibranch_priv()
2046 tcg_gen_ori_i64(dest, dest, ctx->privilege); in do_ibranch_priv()
2063 assert(ctx->iaq_f.disp == 0); in do_page_zero()
2068 switch (ctx->null_cond.c) { in do_page_zero()
2076 TB, we should know the state of PSW[N] from TB->FLAGS. */ in do_page_zero()
2081 if (ctx->psw_xb & PSW_B) { in do_page_zero()
2085 switch (ctx->base.pc_first) { in do_page_zero()
2088 ctx->base.is_jmp = DISAS_NORETURN; in do_page_zero()
2093 ctx->base.is_jmp = DISAS_NORETURN; in do_page_zero()
2104 ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; in do_page_zero()
2110 ctx->base.is_jmp = DISAS_NORETURN; in do_page_zero()
2116 ctx->base.is_jmp = DISAS_NORETURN; in do_page_zero()
2122 static bool trans_nop(DisasContext *ctx, arg_nop *a) in trans_nop() argument
2124 ctx->null_cond = cond_make_f(); in trans_nop()
2128 static bool trans_break(DisasContext *ctx, arg_break *a) in trans_break() argument
2133 static bool trans_sync(DisasContext *ctx, arg_sync *a) in trans_sync() argument
2138 ctx->null_cond = cond_make_f(); in trans_sync()
2142 static bool trans_mfia(DisasContext *ctx, arg_mfia *a) in trans_mfia() argument
2144 TCGv_i64 dest = dest_gpr(ctx, a->t); in trans_mfia()
2146 copy_iaoq_entry(ctx, dest, &ctx->iaq_f); in trans_mfia()
2147 tcg_gen_andi_i64(dest, dest, -4); in trans_mfia()
2149 save_gpr(ctx, a->t, dest); in trans_mfia()
2150 ctx->null_cond = cond_make_f(); in trans_mfia()
2154 static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) in trans_mfsp() argument
2156 unsigned rt = a->t; in trans_mfsp()
2157 unsigned rs = a->sp; in trans_mfsp()
2165 ctx->null_cond = cond_make_f(); in trans_mfsp()
2169 static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) in trans_mfctl() argument
2171 unsigned rt = a->t; in trans_mfctl()
2172 unsigned ctl = a->r; in trans_mfctl()
2177 if (a->e == 0) { in trans_mfctl()
2190 if (translator_io_start(&ctx->base)) { in trans_mfctl()
2191 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_mfctl()
2210 ctx->null_cond = cond_make_f(); in trans_mfctl()
2214 static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a) in trans_mtsp() argument
2216 unsigned rr = a->r; in trans_mtsp()
2217 unsigned rs = a->sp; in trans_mtsp()
2230 ctx->tb_flags &= ~TB_FLAG_SR_SAME; in trans_mtsp()
2238 static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) in trans_mtctl() argument
2240 unsigned ctl = a->t; in trans_mtctl()
2245 reg = load_gpr(ctx, a->r); in trans_mtctl()
2247 tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31); in trans_mtctl()
2250 ctx->null_cond = cond_make_f(); in trans_mtctl()
2254 /* All other control registers are privileged or read-only. */ in trans_mtctl()
2260 if (ctx->is_pa20) { in trans_mtctl()
2261 reg = load_gpr(ctx, a->r); in trans_mtctl()
2264 tcg_gen_ext32u_i64(reg, load_gpr(ctx, a->r)); in trans_mtctl()
2269 if (translator_io_start(&ctx->base)) { in trans_mtctl()
2270 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_mtctl()
2276 translator_io_start(&ctx->base); in trans_mtctl()
2278 /* Exit to re-evaluate interrupts in the main loop. */ in trans_mtctl()
2279 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_mtctl()
2288 offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); in trans_mtctl()
2291 offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); in trans_mtctl()
2305 /* Exit to re-evaluate interrupts in the main loop. */ in trans_mtctl()
2306 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_mtctl()
2316 static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) in trans_mtsarcm() argument
2320 tcg_gen_not_i64(tmp, load_gpr(ctx, a->r)); in trans_mtsarcm()
2321 tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31); in trans_mtsarcm()
2324 ctx->null_cond = cond_make_f(); in trans_mtsarcm()
2328 static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) in trans_ldsid() argument
2330 TCGv_i64 dest = dest_gpr(ctx, a->t); in trans_ldsid()
2336 tcg_gen_mov_i64(dest, space_select(ctx, a->sp, load_gpr(ctx, a->b))); in trans_ldsid()
2339 save_gpr(ctx, a->t, dest); in trans_ldsid()
2341 ctx->null_cond = cond_make_f(); in trans_ldsid()
2345 static bool trans_rsm(DisasContext *ctx, arg_rsm *a) in trans_rsm() argument
2352 /* HP-UX 11i and HP ODE use rsm for read-access to PSW */ in trans_rsm()
2353 if (a->i) { in trans_rsm()
2361 tcg_gen_andi_i64(tmp, tmp, ~a->i); in trans_rsm()
2363 save_gpr(ctx, a->t, tmp); in trans_rsm()
2366 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_rsm()
2371 static bool trans_ssm(DisasContext *ctx, arg_ssm *a) in trans_ssm() argument
2381 tcg_gen_ori_i64(tmp, tmp, a->i); in trans_ssm()
2383 save_gpr(ctx, a->t, tmp); in trans_ssm()
2386 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_ssm()
2391 static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) in trans_mtsm() argument
2398 reg = load_gpr(ctx, a->r); in trans_mtsm()
2403 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_mtsm()
2421 ctx->base.is_jmp = DISAS_NORETURN; in do_rfi()
2427 static bool trans_rfi(DisasContext *ctx, arg_rfi *a) in trans_rfi() argument
2432 static bool trans_rfi_r(DisasContext *ctx, arg_rfi_r *a) in trans_rfi_r() argument
2437 static bool trans_halt(DisasContext *ctx, arg_halt *a) in trans_halt() argument
2444 ctx->base.is_jmp = DISAS_NORETURN; in trans_halt()
2449 static bool trans_reset(DisasContext *ctx, arg_reset *a) in trans_reset() argument
2456 ctx->base.is_jmp = DISAS_NORETURN; in trans_reset()
2489 static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a) in trans_getshadowregs() argument
2494 static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) in trans_nop_addrx() argument
2496 if (a->m) { in trans_nop_addrx()
2497 TCGv_i64 dest = dest_gpr(ctx, a->b); in trans_nop_addrx()
2498 TCGv_i64 src1 = load_gpr(ctx, a->b); in trans_nop_addrx()
2499 TCGv_i64 src2 = load_gpr(ctx, a->x); in trans_nop_addrx()
2503 save_gpr(ctx, a->b, dest); in trans_nop_addrx()
2505 ctx->null_cond = cond_make_f(); in trans_nop_addrx()
2509 static bool trans_fic(DisasContext *ctx, arg_ldst *a) in trans_fic() argument
2512 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_fic()
2513 return trans_nop_addrx(ctx, a); in trans_fic()
2516 static bool trans_probe(DisasContext *ctx, arg_probe *a) in trans_probe() argument
2524 dest = dest_gpr(ctx, a->t); in trans_probe()
2525 form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); in trans_probe()
2527 if (a->imm) { in trans_probe()
2528 level = tcg_constant_i32(a->ri & 3); in trans_probe()
2531 tcg_gen_extrl_i64_i32(level, load_gpr(ctx, a->ri)); in trans_probe()
2534 want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); in trans_probe()
2538 save_gpr(ctx, a->t, dest); in trans_probe()
2542 static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a) in trans_ixtlbx() argument
2544 if (ctx->is_pa20) { in trans_ixtlbx()
2554 form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); in trans_ixtlbx()
2555 reg = load_gpr(ctx, a->r); in trans_ixtlbx()
2556 if (a->addr) { in trans_ixtlbx()
2563 if (ctx->tb_flags & PSW_C) { in trans_ixtlbx()
2564 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_ixtlbx()
2570 static bool do_pxtlb(DisasContext *ctx, arg_ldst *a, bool local) in do_pxtlb() argument
2579 form_gva(ctx, &addr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); in do_pxtlb()
2586 if (ctx->is_pa20) { in do_pxtlb()
2587 tcg_gen_deposit_i64(addr, addr, load_gpr(ctx, a->b), 0, 4); in do_pxtlb()
2596 if (a->m) { in do_pxtlb()
2597 save_gpr(ctx, a->b, ofs); in do_pxtlb()
2601 if (ctx->tb_flags & PSW_C) { in do_pxtlb()
2602 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in do_pxtlb()
2608 static bool trans_pxtlb(DisasContext *ctx, arg_ldst *a) in trans_pxtlb() argument
2610 return do_pxtlb(ctx, a, false); in trans_pxtlb()
2613 static bool trans_pxtlb_l(DisasContext *ctx, arg_ldst *a) in trans_pxtlb_l() argument
2615 return ctx->is_pa20 && do_pxtlb(ctx, a, true); in trans_pxtlb_l()
2618 static bool trans_pxtlbe(DisasContext *ctx, arg_ldst *a) in trans_pxtlbe() argument
2624 trans_nop_addrx(ctx, a); in trans_pxtlbe()
2628 if (ctx->tb_flags & PSW_C) { in trans_pxtlbe()
2629 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_pxtlbe()
2638 * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
2639 * page 13-9 (195/206)
2641 static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a) in trans_ixtlbxf() argument
2643 if (ctx->is_pa20) { in trans_ixtlbxf()
2664 a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) in trans_ixtlbxf()
2667 a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) in trans_ixtlbxf()
2672 reg = load_gpr(ctx, a->r); in trans_ixtlbxf()
2673 if (a->addr) { in trans_ixtlbxf()
2680 if (ctx->tb_flags & PSW_C) { in trans_ixtlbxf()
2681 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_ixtlbxf()
2687 static bool trans_ixtlbt(DisasContext *ctx, arg_ixtlbt *a) in trans_ixtlbt() argument
2689 if (!ctx->is_pa20) { in trans_ixtlbt()
2696 TCGv_i64 src1 = load_gpr(ctx, a->r1); in trans_ixtlbt()
2697 TCGv_i64 src2 = load_gpr(ctx, a->r2); in trans_ixtlbt()
2699 if (a->data) { in trans_ixtlbt()
2706 if (ctx->tb_flags & PSW_C) { in trans_ixtlbt()
2707 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in trans_ixtlbt()
2713 static bool trans_lpa(DisasContext *ctx, arg_ldst *a) in trans_lpa() argument
2722 form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); in trans_lpa()
2728 if (a->m) { in trans_lpa()
2729 save_gpr(ctx, a->b, ofs); in trans_lpa()
2731 save_gpr(ctx, a->t, paddr); in trans_lpa()
2737 static bool trans_lci(DisasContext *ctx, arg_lci *a) in trans_lci() argument
2741 /* The Coherence Index is an implementation-defined function of the in trans_lci()
2742 physical address. Two addresses with the same CI have a coherent in trans_lci()
2745 save_gpr(ctx, a->t, ctx->zero); in trans_lci()
2747 ctx->null_cond = cond_make_f(); in trans_lci()
2751 static bool trans_add(DisasContext *ctx, arg_rrr_cf_d_sh *a) in trans_add() argument
2753 return do_add_reg(ctx, a, false, false, false, false); in trans_add()
2756 static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_d_sh *a) in trans_add_l() argument
2758 return do_add_reg(ctx, a, true, false, false, false); in trans_add_l()
2761 static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a) in trans_add_tsv() argument
2763 return do_add_reg(ctx, a, false, true, false, false); in trans_add_tsv()
2766 static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_d_sh *a) in trans_add_c() argument
2768 return do_add_reg(ctx, a, false, false, false, true); in trans_add_c()
2771 static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a) in trans_add_c_tsv() argument
2773 return do_add_reg(ctx, a, false, true, false, true); in trans_add_c_tsv()
2776 static bool trans_sub(DisasContext *ctx, arg_rrr_cf_d *a) in trans_sub() argument
2778 return do_sub_reg(ctx, a, false, false, false); in trans_sub()
2781 static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf_d *a) in trans_sub_tsv() argument
2783 return do_sub_reg(ctx, a, true, false, false); in trans_sub_tsv()
2786 static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf_d *a) in trans_sub_tc() argument
2788 return do_sub_reg(ctx, a, false, false, true); in trans_sub_tc()
2791 static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf_d *a) in trans_sub_tsv_tc() argument
2793 return do_sub_reg(ctx, a, true, false, true); in trans_sub_tsv_tc()
2796 static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf_d *a) in trans_sub_b() argument
2798 return do_sub_reg(ctx, a, false, true, false); in trans_sub_b()
2801 static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf_d *a) in trans_sub_b_tsv() argument
2803 return do_sub_reg(ctx, a, true, true, false); in trans_sub_b_tsv()
2806 static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a) in trans_andcm() argument
2808 return do_log_reg(ctx, a, tcg_gen_andc_i64); in trans_andcm()
2811 static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a) in trans_and() argument
2813 return do_log_reg(ctx, a, tcg_gen_and_i64); in trans_and()
2816 static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) in trans_or() argument
2818 if (a->cf == 0) { in trans_or()
2819 unsigned r2 = a->r2; in trans_or()
2820 unsigned r1 = a->r1; in trans_or()
2821 unsigned rt = a->t; in trans_or()
2824 ctx->null_cond = cond_make_f(); in trans_or()
2835 ctx->null_cond = cond_make_f(); in trans_or()
2841 * or %r10,%r10,%r10 -- idle loop; wait for interrupt in trans_or()
2842 * or %r31,%r31,%r31 -- death loop; offline cpu in trans_or()
2854 install_iaq_entries(ctx, &ctx->iaq_b, NULL); in trans_or()
2859 offsetof(CPUState, halted) - offsetof(HPPACPU, env)); in trans_or()
2861 ctx->base.is_jmp = DISAS_NORETURN; in trans_or()
2867 return do_log_reg(ctx, a, tcg_gen_or_i64); in trans_or()
2870 static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a) in trans_xor() argument
2872 return do_log_reg(ctx, a, tcg_gen_xor_i64); in trans_xor()
2875 static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a) in trans_cmpclr() argument
2879 if (a->cf) { in trans_cmpclr()
2882 tcg_r1 = load_gpr(ctx, a->r1); in trans_cmpclr()
2883 tcg_r2 = load_gpr(ctx, a->r2); in trans_cmpclr()
2884 do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d); in trans_cmpclr()
2888 static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) in trans_uxor() argument
2892 if (a->cf) { in trans_uxor()
2896 tcg_r1 = load_gpr(ctx, a->r1); in trans_uxor()
2897 tcg_r2 = load_gpr(ctx, a->r2); in trans_uxor()
2898 dest = dest_gpr(ctx, a->t); in trans_uxor()
2901 save_gpr(ctx, a->t, dest); in trans_uxor()
2903 ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest); in trans_uxor()
2907 static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) in do_uaddcm() argument
2911 if (a->cf == 0) { in do_uaddcm()
2912 tcg_r2 = load_gpr(ctx, a->r2); in do_uaddcm()
2913 tmp = dest_gpr(ctx, a->t); in do_uaddcm()
2915 if (a->r1 == 0) { in do_uaddcm()
2920 * Recall that r1 - r2 == r1 + ~r2 + 1. in do_uaddcm()
2921 * Thus r1 + ~r2 == r1 - r2 - 1, in do_uaddcm()
2924 tcg_r1 = load_gpr(ctx, a->r1); in do_uaddcm()
2928 save_gpr(ctx, a->t, tmp); in do_uaddcm()
2929 ctx->null_cond = cond_make_f(); in do_uaddcm()
2934 tcg_r1 = load_gpr(ctx, a->r1); in do_uaddcm()
2935 tcg_r2 = load_gpr(ctx, a->r2); in do_uaddcm()
2938 do_unit_addsub(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, true); in do_uaddcm()
2942 static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a) in trans_uaddcm() argument
2944 return do_uaddcm(ctx, a, false); in trans_uaddcm()
2947 static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf_d *a) in trans_uaddcm_tc() argument
2949 return do_uaddcm(ctx, a, true); in trans_uaddcm_tc()
2952 static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) in do_dcor() argument
2965 do_unit_addsub(ctx, a->t, load_gpr(ctx, a->r), tmp, in do_dcor()
2966 a->cf, a->d, false, is_i); in do_dcor()
2970 static bool trans_dcor(DisasContext *ctx, arg_rr_cf_d *a) in trans_dcor() argument
2972 return do_dcor(ctx, a, false); in trans_dcor()
2975 static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a) in trans_dcor_i() argument
2977 return do_dcor(ctx, a, true); in trans_dcor_i()
2980 static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) in trans_ds() argument
2986 in1 = load_gpr(ctx, a->r1); in trans_ds()
2987 in2 = load_gpr(ctx, a->r2); in trans_ds()
3011 save_gpr(ctx, a->t, dest); in trans_ds()
3026 if (a->cf) { in trans_ds()
3028 if (cond_need_sv(a->cf >> 1)) { in trans_ds()
3030 } else if (cond_need_cb(a->cf >> 1)) { in trans_ds()
3033 ctx->null_cond = do_cond(ctx, a->cf, false, dest, uv, sv); in trans_ds()
3039 static bool trans_addi(DisasContext *ctx, arg_rri_cf *a) in trans_addi() argument
3041 return do_add_imm(ctx, a, false, false); in trans_addi()
3044 static bool trans_addi_tsv(DisasContext *ctx, arg_rri_cf *a) in trans_addi_tsv() argument
3046 return do_add_imm(ctx, a, true, false); in trans_addi_tsv()
3049 static bool trans_addi_tc(DisasContext *ctx, arg_rri_cf *a) in trans_addi_tc() argument
3051 return do_add_imm(ctx, a, false, true); in trans_addi_tc()
3054 static bool trans_addi_tc_tsv(DisasContext *ctx, arg_rri_cf *a) in trans_addi_tc_tsv() argument
3056 return do_add_imm(ctx, a, true, true); in trans_addi_tc_tsv()
3059 static bool trans_subi(DisasContext *ctx, arg_rri_cf *a) in trans_subi() argument
3061 return do_sub_imm(ctx, a, false); in trans_subi()
3064 static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a) in trans_subi_tsv() argument
3066 return do_sub_imm(ctx, a, true); in trans_subi_tsv()
3069 static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a) in trans_cmpiclr() argument
3073 if (a->cf) { in trans_cmpiclr()
3077 tcg_im = tcg_constant_i64(a->i); in trans_cmpiclr()
3078 tcg_r2 = load_gpr(ctx, a->r); in trans_cmpiclr()
3079 do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf, a->d); in trans_cmpiclr()
3084 static bool do_multimedia(DisasContext *ctx, arg_rrr *a, in do_multimedia() argument
3089 if (!ctx->is_pa20) { in do_multimedia()
3095 r1 = load_gpr(ctx, a->r1); in do_multimedia()
3096 r2 = load_gpr(ctx, a->r2); in do_multimedia()
3097 dest = dest_gpr(ctx, a->t); in do_multimedia()
3100 save_gpr(ctx, a->t, dest); in do_multimedia()
3105 static bool do_multimedia_sh(DisasContext *ctx, arg_rri *a, in do_multimedia_sh() argument
3110 if (!ctx->is_pa20) { in do_multimedia_sh()
3116 r = load_gpr(ctx, a->r); in do_multimedia_sh()
3117 dest = dest_gpr(ctx, a->t); in do_multimedia_sh()
3119 fn(dest, r, a->i); in do_multimedia_sh()
3120 save_gpr(ctx, a->t, dest); in do_multimedia_sh()
3125 static bool do_multimedia_shadd(DisasContext *ctx, arg_rrr_sh *a, in do_multimedia_shadd() argument
3131 if (!ctx->is_pa20) { in do_multimedia_shadd()
3137 r1 = load_gpr(ctx, a->r1); in do_multimedia_shadd()
3138 r2 = load_gpr(ctx, a->r2); in do_multimedia_shadd()
3139 dest = dest_gpr(ctx, a->t); in do_multimedia_shadd()
3141 fn(dest, r1, r2, tcg_constant_i32(a->sh)); in do_multimedia_shadd()
3142 save_gpr(ctx, a->t, dest); in do_multimedia_shadd()
3147 static bool trans_hadd(DisasContext *ctx, arg_rrr *a) in trans_hadd() argument
3149 return do_multimedia(ctx, a, tcg_gen_vec_add16_i64); in trans_hadd()
3152 static bool trans_hadd_ss(DisasContext *ctx, arg_rrr *a) in trans_hadd_ss() argument
3154 return do_multimedia(ctx, a, gen_helper_hadd_ss); in trans_hadd_ss()
3157 static bool trans_hadd_us(DisasContext *ctx, arg_rrr *a) in trans_hadd_us() argument
3159 return do_multimedia(ctx, a, gen_helper_hadd_us); in trans_hadd_us()
3162 static bool trans_havg(DisasContext *ctx, arg_rrr *a) in trans_havg() argument
3164 return do_multimedia(ctx, a, gen_helper_havg); in trans_havg()
3167 static bool trans_hshl(DisasContext *ctx, arg_rri *a) in trans_hshl() argument
3169 return do_multimedia_sh(ctx, a, tcg_gen_vec_shl16i_i64); in trans_hshl()
3172 static bool trans_hshr_s(DisasContext *ctx, arg_rri *a) in trans_hshr_s() argument
3174 return do_multimedia_sh(ctx, a, tcg_gen_vec_sar16i_i64); in trans_hshr_s()
3177 static bool trans_hshr_u(DisasContext *ctx, arg_rri *a) in trans_hshr_u() argument
3179 return do_multimedia_sh(ctx, a, tcg_gen_vec_shr16i_i64); in trans_hshr_u()
3182 static bool trans_hshladd(DisasContext *ctx, arg_rrr_sh *a) in trans_hshladd() argument
3184 return do_multimedia_shadd(ctx, a, gen_helper_hshladd); in trans_hshladd()
3187 static bool trans_hshradd(DisasContext *ctx, arg_rrr_sh *a) in trans_hshradd() argument
3189 return do_multimedia_shadd(ctx, a, gen_helper_hshradd); in trans_hshradd()
3192 static bool trans_hsub(DisasContext *ctx, arg_rrr *a) in trans_hsub() argument
3194 return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64); in trans_hsub()
3197 static bool trans_hsub_ss(DisasContext *ctx, arg_rrr *a) in trans_hsub_ss() argument
3199 return do_multimedia(ctx, a, gen_helper_hsub_ss); in trans_hsub_ss()
3202 static bool trans_hsub_us(DisasContext *ctx, arg_rrr *a) in trans_hsub_us() argument
3204 return do_multimedia(ctx, a, gen_helper_hsub_us); in trans_hsub_us()
3218 static bool trans_mixh_l(DisasContext *ctx, arg_rrr *a) in trans_mixh_l() argument
3220 return do_multimedia(ctx, a, gen_mixh_l); in trans_mixh_l()
3234 static bool trans_mixh_r(DisasContext *ctx, arg_rrr *a) in trans_mixh_r() argument
3236 return do_multimedia(ctx, a, gen_mixh_r); in trans_mixh_r()
3247 static bool trans_mixw_l(DisasContext *ctx, arg_rrr *a) in trans_mixw_l() argument
3249 return do_multimedia(ctx, a, gen_mixw_l); in trans_mixw_l()
3257 static bool trans_mixw_r(DisasContext *ctx, arg_rrr *a) in trans_mixw_r() argument
3259 return do_multimedia(ctx, a, gen_mixw_r); in trans_mixw_r()
3262 static bool trans_permh(DisasContext *ctx, arg_permh *a) in trans_permh() argument
3266 if (!ctx->is_pa20) { in trans_permh()
3272 r = load_gpr(ctx, a->r1); in trans_permh()
3278 tcg_gen_extract_i64(t0, r, (3 - a->c0) * 16, 16); in trans_permh()
3279 tcg_gen_extract_i64(t1, r, (3 - a->c1) * 16, 16); in trans_permh()
3280 tcg_gen_extract_i64(t2, r, (3 - a->c2) * 16, 16); in trans_permh()
3281 tcg_gen_extract_i64(t3, r, (3 - a->c3) * 16, 16); in trans_permh()
3287 save_gpr(ctx, a->t, t0); in trans_permh()
3291 static bool trans_ld(DisasContext *ctx, arg_ldst *a) in trans_ld() argument
3293 if (ctx->is_pa20) { in trans_ld()
3298 if (a->t == 0) { in trans_ld()
3299 return trans_nop_addrx(ctx, a); in trans_ld()
3301 } else if (a->size > MO_32) { in trans_ld()
3304 return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, in trans_ld()
3305 a->disp, a->sp, a->m, a->size | MO_TE); in trans_ld()
3308 static bool trans_st(DisasContext *ctx, arg_ldst *a) in trans_st() argument
3310 assert(a->x == 0 && a->scale == 0); in trans_st()
3311 if (!ctx->is_pa20 && a->size > MO_32) { in trans_st()
3314 return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE); in trans_st()
3317 static bool trans_ldc(DisasContext *ctx, arg_ldst *a) in trans_ldc() argument
3319 MemOp mop = MO_TE | MO_ALIGN | a->size; in trans_ldc()
3323 if (!ctx->is_pa20 && a->size > MO_32) { in trans_ldc()
3329 if (a->m) { in trans_ldc()
3334 dest = dest_gpr(ctx, a->t); in trans_ldc()
3337 form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? 3 : 0, in trans_ldc()
3338 a->disp, a->sp, a->m, MMU_DISABLED(ctx)); in trans_ldc()
3343 * Detect this case and log a GUEST_ERROR. in trans_ldc()
3345 * TODO: HPPA64 relaxes the over-alignment requirement in trans_ldc()
3350 tcg_gen_atomic_xchg_i64(dest, addr, ctx->zero, ctx->mmu_idx, mop); in trans_ldc()
3352 if (a->m) { in trans_ldc()
3353 save_gpr(ctx, a->b, ofs); in trans_ldc()
3355 save_gpr(ctx, a->t, dest); in trans_ldc()
3360 static bool trans_stby(DisasContext *ctx, arg_stby *a) in trans_stby() argument
3367 form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, in trans_stby()
3369 val = load_gpr(ctx, a->r); in trans_stby()
3370 if (a->a) { in trans_stby()
3371 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in trans_stby()
3377 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in trans_stby()
3383 if (a->m) { in trans_stby()
3385 save_gpr(ctx, a->b, ofs); in trans_stby()
3391 static bool trans_stdby(DisasContext *ctx, arg_stby *a) in trans_stdby() argument
3396 if (!ctx->is_pa20) { in trans_stdby()
3401 form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, in trans_stdby()
3403 val = load_gpr(ctx, a->r); in trans_stdby()
3404 if (a->a) { in trans_stdby()
3405 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in trans_stdby()
3411 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { in trans_stdby()
3417 if (a->m) { in trans_stdby()
3419 save_gpr(ctx, a->b, ofs); in trans_stdby()
3425 static bool trans_lda(DisasContext *ctx, arg_ldst *a) in trans_lda() argument
3427 int hold_mmu_idx = ctx->mmu_idx; in trans_lda()
3430 ctx->mmu_idx = ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; in trans_lda()
3431 trans_ld(ctx, a); in trans_lda()
3432 ctx->mmu_idx = hold_mmu_idx; in trans_lda()
3436 static bool trans_sta(DisasContext *ctx, arg_ldst *a) in trans_sta() argument
3438 int hold_mmu_idx = ctx->mmu_idx; in trans_sta()
3441 ctx->mmu_idx = ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; in trans_sta()
3442 trans_st(ctx, a); in trans_sta()
3443 ctx->mmu_idx = hold_mmu_idx; in trans_sta()
3447 static bool trans_ldil(DisasContext *ctx, arg_ldil *a) in trans_ldil() argument
3449 TCGv_i64 tcg_rt = dest_gpr(ctx, a->t); in trans_ldil()
3451 tcg_gen_movi_i64(tcg_rt, a->i); in trans_ldil()
3452 save_gpr(ctx, a->t, tcg_rt); in trans_ldil()
3453 ctx->null_cond = cond_make_f(); in trans_ldil()
3457 static bool trans_addil(DisasContext *ctx, arg_addil *a) in trans_addil() argument
3459 TCGv_i64 tcg_rt = load_gpr(ctx, a->r); in trans_addil()
3462 tcg_gen_addi_i64(tcg_r1, tcg_rt, a->i); in trans_addil()
3464 ctx->null_cond = cond_make_f(); in trans_addil()
3468 static bool trans_ldo(DisasContext *ctx, arg_ldo *a) in trans_ldo() argument
3470 TCGv_i64 tcg_rt = dest_gpr(ctx, a->t); in trans_ldo()
3472 /* Special case rb == 0, for the LDI pseudo-op. in trans_ldo()
3473 The COPY pseudo-op is handled for free within tcg_gen_addi_i64. */ in trans_ldo()
3474 if (a->b == 0) { in trans_ldo()
3475 tcg_gen_movi_i64(tcg_rt, a->i); in trans_ldo()
3477 tcg_gen_addi_i64(tcg_rt, cpu_gr[a->b], a->i); in trans_ldo()
3479 save_gpr(ctx, a->t, tcg_rt); in trans_ldo()
3480 ctx->null_cond = cond_make_f(); in trans_ldo()
3504 static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a) in trans_cmpb() argument
3506 if (!ctx->is_pa20 && a->d) { in trans_cmpb()
3510 return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), in trans_cmpb()
3511 a->c, a->f, a->d, a->n, a->disp); in trans_cmpb()
3514 static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) in trans_cmpbi() argument
3516 if (!ctx->is_pa20 && a->d) { in trans_cmpbi()
3520 return do_cmpb(ctx, a->r, tcg_constant_i64(a->i), in trans_cmpbi()
3521 a->c, a->f, a->d, a->n, a->disp); in trans_cmpbi()
3533 * dropping ZNV, SV, OD in favor of double-word EQ, LT, LE. in do_addb()
3535 if (ctx->tb_flags & PSW_W) { in do_addb()
3551 tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero); in do_addb()
3567 static bool trans_addb(DisasContext *ctx, arg_addb *a) in trans_addb() argument
3570 return do_addb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); in trans_addb()
3573 static bool trans_addbi(DisasContext *ctx, arg_addbi *a) in trans_addbi() argument
3576 return do_addb(ctx, a->r, tcg_constant_i64(a->i), a->c, a->f, a->n, a->disp); in trans_addbi()
3579 static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) in trans_bb_sar() argument
3587 tcg_r = load_gpr(ctx, a->r); in trans_bb_sar()
3588 if (a->d) { in trans_bb_sar()
3596 cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); in trans_bb_sar()
3597 return do_cbranch(ctx, a->disp, a->n, &cond); in trans_bb_sar()
3600 static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) in trans_bb_imm() argument
3603 int p = a->p | (a->d ? 0 : 32); in trans_bb_imm()
3606 cond = cond_make_vi(a->c ? TCG_COND_TSTEQ : TCG_COND_TSTNE, in trans_bb_imm()
3607 load_gpr(ctx, a->r), 1ull << (63 - p)); in trans_bb_imm()
3608 return do_cbranch(ctx, a->disp, a->n, &cond); in trans_bb_imm()
3611 static bool trans_movb(DisasContext *ctx, arg_movb *a) in trans_movb() argument
3618 dest = dest_gpr(ctx, a->r2); in trans_movb()
3619 if (a->r1 == 0) { in trans_movb()
3622 tcg_gen_mov_i64(dest, cpu_gr[a->r1]); in trans_movb()
3625 /* All MOVB conditions are 32-bit. */ in trans_movb()
3626 cond = do_sed_cond(ctx, a->c, false, dest); in trans_movb()
3627 return do_cbranch(ctx, a->disp, a->n, &cond); in trans_movb()
3630 static bool trans_movbi(DisasContext *ctx, arg_movbi *a) in trans_movbi() argument
3637 dest = dest_gpr(ctx, a->r); in trans_movbi()
3638 tcg_gen_movi_i64(dest, a->i); in trans_movbi()
3640 /* All MOVBI conditions are 32-bit. */ in trans_movbi()
3641 cond = do_sed_cond(ctx, a->c, false, dest); in trans_movbi()
3642 return do_cbranch(ctx, a->disp, a->n, &cond); in trans_movbi()
3645 static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) in trans_shrp_sar() argument
3649 if (!ctx->is_pa20 && a->d) { in trans_shrp_sar()
3652 if (a->c) { in trans_shrp_sar()
3656 dest = dest_gpr(ctx, a->t); in trans_shrp_sar()
3657 src2 = load_gpr(ctx, a->r2); in trans_shrp_sar()
3658 if (a->r1 == 0) { in trans_shrp_sar()
3659 if (a->d) { in trans_shrp_sar()
3668 } else if (a->r1 == a->r2) { in trans_shrp_sar()
3669 if (a->d) { in trans_shrp_sar()
3682 TCGv_i64 src1 = load_gpr(ctx, a->r1); in trans_shrp_sar()
3684 if (a->d) { in trans_shrp_sar()
3702 save_gpr(ctx, a->t, dest); in trans_shrp_sar()
3705 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_shrp_sar()
3709 static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a) in trans_shrp_imm() argument
3714 if (!ctx->is_pa20 && a->d) { in trans_shrp_imm()
3717 if (a->c) { in trans_shrp_imm()
3721 width = a->d ? 64 : 32; in trans_shrp_imm()
3722 sa = width - 1 - a->cpos; in trans_shrp_imm()
3724 dest = dest_gpr(ctx, a->t); in trans_shrp_imm()
3725 t2 = load_gpr(ctx, a->r2); in trans_shrp_imm()
3726 if (a->r1 == 0) { in trans_shrp_imm()
3727 tcg_gen_extract_i64(dest, t2, sa, width - sa); in trans_shrp_imm()
3729 tcg_gen_extract2_i64(dest, t2, cpu_gr[a->r1], sa); in trans_shrp_imm()
3731 assert(!a->d); in trans_shrp_imm()
3732 if (a->r1 == a->r2) { in trans_shrp_imm()
3738 tcg_gen_concat32_i64(dest, t2, cpu_gr[a->r1]); in trans_shrp_imm()
3742 save_gpr(ctx, a->t, dest); in trans_shrp_imm()
3745 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_shrp_imm()
3749 static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a) in trans_extr_sar() argument
3751 unsigned widthm1 = a->d ? 63 : 31; in trans_extr_sar()
3754 if (!ctx->is_pa20 && a->d) { in trans_extr_sar()
3757 if (a->c) { in trans_extr_sar()
3761 dest = dest_gpr(ctx, a->t); in trans_extr_sar()
3762 src = load_gpr(ctx, a->r); in trans_extr_sar()
3765 /* Recall that SAR is using big-endian bit numbering. */ in trans_extr_sar()
3769 if (a->se) { in trans_extr_sar()
3770 if (!a->d) { in trans_extr_sar()
3775 tcg_gen_sextract_i64(dest, dest, 0, a->len); in trans_extr_sar()
3777 if (!a->d) { in trans_extr_sar()
3782 tcg_gen_extract_i64(dest, dest, 0, a->len); in trans_extr_sar()
3784 save_gpr(ctx, a->t, dest); in trans_extr_sar()
3787 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_extr_sar()
3791 static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a) in trans_extr_imm() argument
3796 if (!ctx->is_pa20 && a->d) { in trans_extr_imm()
3799 if (a->c) { in trans_extr_imm()
3803 len = a->len; in trans_extr_imm()
3804 width = a->d ? 64 : 32; in trans_extr_imm()
3805 cpos = width - 1 - a->pos; in trans_extr_imm()
3807 len = width - cpos; in trans_extr_imm()
3810 dest = dest_gpr(ctx, a->t); in trans_extr_imm()
3811 src = load_gpr(ctx, a->r); in trans_extr_imm()
3812 if (a->se) { in trans_extr_imm()
3817 save_gpr(ctx, a->t, dest); in trans_extr_imm()
3820 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_extr_imm()
3824 static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) in trans_depi_imm() argument
3830 if (!ctx->is_pa20 && a->d) { in trans_depi_imm()
3833 if (a->c) { in trans_depi_imm()
3837 len = a->len; in trans_depi_imm()
3838 width = a->d ? 64 : 32; in trans_depi_imm()
3839 if (a->cpos + len > width) { in trans_depi_imm()
3840 len = width - a->cpos; in trans_depi_imm()
3843 dest = dest_gpr(ctx, a->t); in trans_depi_imm()
3844 mask0 = deposit64(0, a->cpos, len, a->i); in trans_depi_imm()
3845 mask1 = deposit64(-1, a->cpos, len, a->i); in trans_depi_imm()
3847 if (a->nz) { in trans_depi_imm()
3848 TCGv_i64 src = load_gpr(ctx, a->t); in trans_depi_imm()
3854 save_gpr(ctx, a->t, dest); in trans_depi_imm()
3857 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_depi_imm()
3861 static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) in trans_dep_imm() argument
3863 unsigned rs = a->nz ? a->t : 0; in trans_dep_imm()
3867 if (!ctx->is_pa20 && a->d) { in trans_dep_imm()
3870 if (a->c) { in trans_dep_imm()
3874 len = a->len; in trans_dep_imm()
3875 width = a->d ? 64 : 32; in trans_dep_imm()
3876 if (a->cpos + len > width) { in trans_dep_imm()
3877 len = width - a->cpos; in trans_dep_imm()
3880 dest = dest_gpr(ctx, a->t); in trans_dep_imm()
3881 val = load_gpr(ctx, a->r); in trans_dep_imm()
3883 tcg_gen_deposit_z_i64(dest, val, a->cpos, len); in trans_dep_imm()
3885 tcg_gen_deposit_i64(dest, cpu_gr[rs], val, a->cpos, len); in trans_dep_imm()
3887 save_gpr(ctx, a->t, dest); in trans_dep_imm()
3890 ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); in trans_dep_imm()
3900 uint64_t msb = 1ULL << (len - 1); in do_dep_sar()
3906 /* Convert big-endian bit numbering in SAR to left-shift. */ in do_dep_sar()
3911 tcg_gen_movi_i64(mask, msb + (msb - 1)); in do_dep_sar()
3924 ctx->null_cond = do_sed_cond(ctx, c, d, dest); in do_dep_sar()
3928 static bool trans_dep_sar(DisasContext *ctx, arg_dep_sar *a) in trans_dep_sar() argument
3930 if (!ctx->is_pa20 && a->d) { in trans_dep_sar()
3933 if (a->c) { in trans_dep_sar()
3936 return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, in trans_dep_sar()
3937 load_gpr(ctx, a->r)); in trans_dep_sar()
3940 static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a) in trans_depi_sar() argument
3942 if (!ctx->is_pa20 && a->d) { in trans_depi_sar()
3945 if (a->c) { in trans_depi_sar()
3948 return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, in trans_depi_sar()
3949 tcg_constant_i64(a->i)); in trans_depi_sar()
3952 static bool trans_be(DisasContext *ctx, arg_be *a) in trans_be() argument
3955 ctx->iaq_j.space = tcg_temp_new_i64(); in trans_be()
3956 load_spr(ctx, ctx->iaq_j.space, a->sp); in trans_be()
3959 ctx->iaq_j.base = tcg_temp_new_i64(); in trans_be()
3960 ctx->iaq_j.disp = 0; in trans_be()
3962 tcg_gen_addi_i64(ctx->iaq_j.base, load_gpr(ctx, a->b), a->disp); in trans_be()
3963 ctx->iaq_j.base = do_ibranch_priv(ctx, ctx->iaq_j.base); in trans_be()
3965 return do_ibranch(ctx, a->l, true, a->n); in trans_be()
3968 static bool trans_bl(DisasContext *ctx, arg_bl *a) in trans_bl() argument
3970 return do_dbranch(ctx, a->disp, a->l, a->n); in trans_bl()
3973 static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) in trans_b_gate() argument
3975 int64_t disp = a->disp; in trans_b_gate()
3979 if (ctx->psw_xb & PSW_B) { in trans_b_gate()
3986 if (ctx->privilege == 0) { in trans_b_gate()
3988 } else if (!(ctx->tb_flags & PSW_C)) { in trans_b_gate()
3990 disp -= ctx->privilege; in trans_b_gate()
3995 copy_iaoq_entry(ctx, off, &ctx->iaq_f); in trans_b_gate()
3998 ctx->iaq_j.base = off; in trans_b_gate()
3999 ctx->iaq_j.disp = disp + 8; in trans_b_gate()
4004 if (a->l) { in trans_b_gate()
4005 TCGv_i64 tmp = dest_gpr(ctx, a->l); in trans_b_gate()
4006 if (ctx->privilege < 3) { in trans_b_gate()
4007 tcg_gen_andi_i64(tmp, tmp, -4); in trans_b_gate()
4009 tcg_gen_ori_i64(tmp, tmp, ctx->privilege); in trans_b_gate()
4010 save_gpr(ctx, a->l, tmp); in trans_b_gate()
4014 return do_ibranch(ctx, 0, false, a->n); in trans_b_gate()
4016 return do_dbranch(ctx, disp, 0, a->n); in trans_b_gate()
4019 static bool trans_blr(DisasContext *ctx, arg_blr *a) in trans_blr() argument
4021 if (a->x) { in trans_blr()
4022 DisasIAQE next = iaqe_incr(&ctx->iaq_f, 8); in trans_blr()
4028 tcg_gen_shli_i64(t1, load_gpr(ctx, a->x), 3); in trans_blr()
4031 ctx->iaq_j = iaqe_next_absv(ctx, t0); in trans_blr()
4032 return do_ibranch(ctx, a->l, false, a->n); in trans_blr()
4034 /* BLR R0,RX is a good way to load PC+8 into RX. */ in trans_blr()
4035 return do_dbranch(ctx, 0, a->l, a->n); in trans_blr()
4039 static bool trans_bv(DisasContext *ctx, arg_bv *a) in trans_bv() argument
4043 if (a->x == 0) { in trans_bv()
4044 dest = load_gpr(ctx, a->b); in trans_bv()
4047 tcg_gen_shli_i64(dest, load_gpr(ctx, a->x), 3); in trans_bv()
4048 tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); in trans_bv()
4051 ctx->iaq_j = iaqe_next_absv(ctx, dest); in trans_bv()
4053 return do_ibranch(ctx, 0, false, a->n); in trans_bv()
4056 static bool trans_bve(DisasContext *ctx, arg_bve *a) in trans_bve() argument
4058 TCGv_i64 b = load_gpr(ctx, a->b); in trans_bve()
4061 ctx->iaq_j.space = space_select(ctx, 0, b); in trans_bve()
4063 ctx->iaq_j.base = do_ibranch_priv(ctx, b); in trans_bve()
4064 ctx->iaq_j.disp = 0; in trans_bve()
4066 return do_ibranch(ctx, a->l, false, a->n); in trans_bve()
4069 static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) in trans_nopbts() argument
4072 return ctx->is_pa20; in trans_nopbts()
4084 static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a) in trans_fid_f() argument
4088 if (ctx->is_pa20) { in trans_fid_f()
4089 ret = 0x13080000000000ULL; /* PA8700 (PCX-W2) */ in trans_fid_f()
4091 ret = 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */ in trans_fid_f()
4099 static bool trans_fcpy_f(DisasContext *ctx, arg_fclass01 *a) in trans_fcpy_f() argument
4101 return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f); in trans_fcpy_f()
4109 static bool trans_fcpy_d(DisasContext *ctx, arg_fclass01 *a) in trans_fcpy_d() argument
4111 return do_fop_ded(ctx, a->t, a->r, gen_fcpy_d); in trans_fcpy_d()
4119 static bool trans_fabs_f(DisasContext *ctx, arg_fclass01 *a) in trans_fabs_f() argument
4121 return do_fop_wew(ctx, a->t, a->r, gen_fabs_f); in trans_fabs_f()
4129 static bool trans_fabs_d(DisasContext *ctx, arg_fclass01 *a) in trans_fabs_d() argument
4131 return do_fop_ded(ctx, a->t, a->r, gen_fabs_d); in trans_fabs_d()
4134 static bool trans_fsqrt_f(DisasContext *ctx, arg_fclass01 *a) in trans_fsqrt_f() argument
4136 return do_fop_wew(ctx, a->t, a->r, gen_helper_fsqrt_s); in trans_fsqrt_f()
4139 static bool trans_fsqrt_d(DisasContext *ctx, arg_fclass01 *a) in trans_fsqrt_d() argument
4141 return do_fop_ded(ctx, a->t, a->r, gen_helper_fsqrt_d); in trans_fsqrt_d()
4144 static bool trans_frnd_f(DisasContext *ctx, arg_fclass01 *a) in trans_frnd_f() argument
4146 return do_fop_wew(ctx, a->t, a->r, gen_helper_frnd_s); in trans_frnd_f()
4149 static bool trans_frnd_d(DisasContext *ctx, arg_fclass01 *a) in trans_frnd_d() argument
4151 return do_fop_ded(ctx, a->t, a->r, gen_helper_frnd_d); in trans_frnd_d()
4159 static bool trans_fneg_f(DisasContext *ctx, arg_fclass01 *a) in trans_fneg_f() argument
4161 return do_fop_wew(ctx, a->t, a->r, gen_fneg_f); in trans_fneg_f()
4169 static bool trans_fneg_d(DisasContext *ctx, arg_fclass01 *a) in trans_fneg_d() argument
4171 return do_fop_ded(ctx, a->t, a->r, gen_fneg_d); in trans_fneg_d()
4179 static bool trans_fnegabs_f(DisasContext *ctx, arg_fclass01 *a) in trans_fnegabs_f() argument
4181 return do_fop_wew(ctx, a->t, a->r, gen_fnegabs_f); in trans_fnegabs_f()
4189 static bool trans_fnegabs_d(DisasContext *ctx, arg_fclass01 *a) in trans_fnegabs_d() argument
4191 return do_fop_ded(ctx, a->t, a->r, gen_fnegabs_d); in trans_fnegabs_d()
4198 static bool trans_fcnv_d_f(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_d_f() argument
4200 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_s); in trans_fcnv_d_f()
4203 static bool trans_fcnv_f_d(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_f_d() argument
4205 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_d); in trans_fcnv_f_d()
4208 static bool trans_fcnv_w_f(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_w_f() argument
4210 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_w_s); in trans_fcnv_w_f()
4213 static bool trans_fcnv_q_f(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_q_f() argument
4215 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_dw_s); in trans_fcnv_q_f()
4218 static bool trans_fcnv_w_d(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_w_d() argument
4220 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_w_d); in trans_fcnv_w_d()
4223 static bool trans_fcnv_q_d(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_q_d() argument
4225 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_dw_d); in trans_fcnv_q_d()
4228 static bool trans_fcnv_f_w(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_f_w() argument
4230 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_w); in trans_fcnv_f_w()
4233 static bool trans_fcnv_d_w(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_d_w() argument
4235 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_w); in trans_fcnv_d_w()
4238 static bool trans_fcnv_f_q(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_f_q() argument
4240 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_dw); in trans_fcnv_f_q()
4243 static bool trans_fcnv_d_q(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_d_q() argument
4245 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_dw); in trans_fcnv_d_q()
4248 static bool trans_fcnv_t_f_w(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_t_f_w() argument
4250 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_w); in trans_fcnv_t_f_w()
4253 static bool trans_fcnv_t_d_w(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_t_d_w() argument
4255 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_w); in trans_fcnv_t_d_w()
4258 static bool trans_fcnv_t_f_q(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_t_f_q() argument
4260 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_dw); in trans_fcnv_t_f_q()
4263 static bool trans_fcnv_t_d_q(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_t_d_q() argument
4265 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_dw); in trans_fcnv_t_d_q()
4268 static bool trans_fcnv_uw_f(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_uw_f() argument
4270 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_uw_s); in trans_fcnv_uw_f()
4273 static bool trans_fcnv_uq_f(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_uq_f() argument
4275 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_udw_s); in trans_fcnv_uq_f()
4278 static bool trans_fcnv_uw_d(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_uw_d() argument
4280 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_uw_d); in trans_fcnv_uw_d()
4283 static bool trans_fcnv_uq_d(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_uq_d() argument
4285 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_udw_d); in trans_fcnv_uq_d()
4288 static bool trans_fcnv_f_uw(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_f_uw() argument
4290 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_uw); in trans_fcnv_f_uw()
4293 static bool trans_fcnv_d_uw(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_d_uw() argument
4295 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_uw); in trans_fcnv_d_uw()
4298 static bool trans_fcnv_f_uq(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_f_uq() argument
4300 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_udw); in trans_fcnv_f_uq()
4303 static bool trans_fcnv_d_uq(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_d_uq() argument
4305 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_udw); in trans_fcnv_d_uq()
4308 static bool trans_fcnv_t_f_uw(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_t_f_uw() argument
4310 return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_uw); in trans_fcnv_t_f_uw()
4313 static bool trans_fcnv_t_d_uw(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_t_d_uw() argument
4315 return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_uw); in trans_fcnv_t_d_uw()
4318 static bool trans_fcnv_t_f_uq(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_t_f_uq() argument
4320 return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_udw); in trans_fcnv_t_f_uq()
4323 static bool trans_fcnv_t_d_uq(DisasContext *ctx, arg_fclass01 *a) in trans_fcnv_t_d_uq() argument
4325 return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_udw); in trans_fcnv_t_d_uq()
4332 static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a) in trans_fcmp_f() argument
4338 ta = load_frw0_i32(a->r1); in trans_fcmp_f()
4339 tb = load_frw0_i32(a->r2); in trans_fcmp_f()
4340 ty = tcg_constant_i32(a->y); in trans_fcmp_f()
4341 tc = tcg_constant_i32(a->c); in trans_fcmp_f()
4348 static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) in trans_fcmp_d() argument
4355 ta = load_frd0(a->r1); in trans_fcmp_d()
4356 tb = load_frd0(a->r2); in trans_fcmp_d()
4357 ty = tcg_constant_i32(a->y); in trans_fcmp_d()
4358 tc = tcg_constant_i32(a->c); in trans_fcmp_d()
4365 static bool trans_ftest(DisasContext *ctx, arg_ftest *a) in trans_ftest() argument
4376 if (a->y == 1) { in trans_ftest()
4377 switch (a->c) { in trans_ftest()
4407 unsigned cbit = (a->y ^ 1) - 1; in trans_ftest()
4411 ctx->null_cond = cond_make_ti(tc, t, mask); in trans_ftest()
4419 static bool trans_fadd_f(DisasContext *ctx, arg_fclass3 *a) in trans_fadd_f() argument
4421 return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fadd_s); in trans_fadd_f()
4424 static bool trans_fadd_d(DisasContext *ctx, arg_fclass3 *a) in trans_fadd_d() argument
4426 return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fadd_d); in trans_fadd_d()
4429 static bool trans_fsub_f(DisasContext *ctx, arg_fclass3 *a) in trans_fsub_f() argument
4431 return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fsub_s); in trans_fsub_f()
4434 static bool trans_fsub_d(DisasContext *ctx, arg_fclass3 *a) in trans_fsub_d() argument
4436 return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fsub_d); in trans_fsub_d()
4439 static bool trans_fmpy_f(DisasContext *ctx, arg_fclass3 *a) in trans_fmpy_f() argument
4441 return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_s); in trans_fmpy_f()
4444 static bool trans_fmpy_d(DisasContext *ctx, arg_fclass3 *a) in trans_fmpy_d() argument
4446 return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_d); in trans_fmpy_d()
4449 static bool trans_fdiv_f(DisasContext *ctx, arg_fclass3 *a) in trans_fdiv_f() argument
4451 return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_s); in trans_fdiv_f()
4454 static bool trans_fdiv_d(DisasContext *ctx, arg_fclass3 *a) in trans_fdiv_d() argument
4456 return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_d); in trans_fdiv_d()
4459 static bool trans_xmpyu(DisasContext *ctx, arg_xmpyu *a) in trans_xmpyu() argument
4465 x = load_frw0_i64(a->r1); in trans_xmpyu()
4466 y = load_frw0_i64(a->r2); in trans_xmpyu()
4468 save_frd(a->t, x); in trans_xmpyu()
4473 /* Convert the fmpyadd single-precision register encodings to standard. */
4479 static bool do_fmpyadd_s(DisasContext *ctx, arg_mpyadd *a, bool is_sub) in do_fmpyadd_s() argument
4481 int tm = fmpyadd_s_reg(a->tm); in do_fmpyadd_s()
4482 int ra = fmpyadd_s_reg(a->ra); in do_fmpyadd_s()
4483 int ta = fmpyadd_s_reg(a->ta); in do_fmpyadd_s()
4484 int rm2 = fmpyadd_s_reg(a->rm2); in do_fmpyadd_s()
4485 int rm1 = fmpyadd_s_reg(a->rm1); in do_fmpyadd_s()
4496 static bool trans_fmpyadd_f(DisasContext *ctx, arg_mpyadd *a) in trans_fmpyadd_f() argument
4498 return do_fmpyadd_s(ctx, a, false); in trans_fmpyadd_f()
4501 static bool trans_fmpysub_f(DisasContext *ctx, arg_mpyadd *a) in trans_fmpysub_f() argument
4503 return do_fmpyadd_s(ctx, a, true); in trans_fmpysub_f()
4506 static bool do_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a, bool is_sub) in do_fmpyadd_d() argument
4510 do_fop_dedd(ctx, a->tm, a->rm1, a->rm2, gen_helper_fmpy_d); in do_fmpyadd_d()
4511 do_fop_dedd(ctx, a->ta, a->ta, a->ra, in do_fmpyadd_d()
4517 static bool trans_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a) in trans_fmpyadd_d() argument
4519 return do_fmpyadd_d(ctx, a, false); in trans_fmpyadd_d()
4522 static bool trans_fmpysub_d(DisasContext *ctx, arg_mpyadd *a) in trans_fmpysub_d() argument
4524 return do_fmpyadd_d(ctx, a, true); in trans_fmpysub_d()
4527 static bool trans_fmpyfadd_f(DisasContext *ctx, arg_fmpyfadd_f *a) in trans_fmpyfadd_f() argument
4532 x = load_frw0_i32(a->rm1); in trans_fmpyfadd_f()
4533 y = load_frw0_i32(a->rm2); in trans_fmpyfadd_f()
4534 z = load_frw0_i32(a->ra3); in trans_fmpyfadd_f()
4536 if (a->neg) { in trans_fmpyfadd_f()
4542 save_frw_i32(a->t, x); in trans_fmpyfadd_f()
4546 static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a) in trans_fmpyfadd_d() argument
4551 x = load_frd0(a->rm1); in trans_fmpyfadd_d()
4552 y = load_frd0(a->rm2); in trans_fmpyfadd_d()
4553 z = load_frd0(a->ra3); in trans_fmpyfadd_d()
4555 if (a->neg) { in trans_fmpyfadd_d()
4561 save_frd(a->t, x); in trans_fmpyfadd_d()
4565 /* Emulate PDC BTLB, called by SeaBIOS-hppa */
4566 static bool trans_diag_btlb(DisasContext *ctx, arg_diag_btlb *a) in trans_diag_btlb() argument
4576 /* Print char in %r26 to first serial console, used by SeaBIOS-hppa */
4577 static bool trans_diag_cout(DisasContext *ctx, arg_diag_cout *a) in trans_diag_cout() argument
4587 static bool trans_diag_getshadowregs_pa1(DisasContext *ctx, arg_empty *a) in trans_diag_getshadowregs_pa1() argument
4589 return !ctx->is_pa20 && do_getshadowregs(ctx); in trans_diag_getshadowregs_pa1()
4592 static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a) in trans_diag_putshadowregs_pa1() argument
4594 return !ctx->is_pa20 && do_putshadowregs(ctx); in trans_diag_putshadowregs_pa1()
4597 static bool trans_diag_mfdiag(DisasContext *ctx, arg_diag_mfdiag *a) in trans_diag_mfdiag() argument
4601 TCGv_i64 dest = dest_gpr(ctx, a->rt); in trans_diag_mfdiag()
4603 offsetof(CPUHPPAState, dr[a->dr])); in trans_diag_mfdiag()
4604 save_gpr(ctx, a->rt, dest); in trans_diag_mfdiag()
4608 static bool trans_diag_mtdiag(DisasContext *ctx, arg_diag_mtdiag *a) in trans_diag_mtdiag() argument
4612 tcg_gen_st_i64(load_gpr(ctx, a->r1), tcg_env, in trans_diag_mtdiag()
4613 offsetof(CPUHPPAState, dr[a->dr])); in trans_diag_mtdiag()
4615 if (ctx->is_pa20 && (a->dr == 2)) { in trans_diag_mtdiag()
4619 ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; in trans_diag_mtdiag()
4625 static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) in trans_diag_unimp() argument
4628 qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i); in trans_diag_unimp()
4638 ctx->cs = cs; in hppa_tr_init_disas_context()
4639 ctx->tb_flags = ctx->base.tb->flags; in hppa_tr_init_disas_context()
4640 ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); in hppa_tr_init_disas_context()
4641 ctx->psw_xb = ctx->tb_flags & (PSW_X | PSW_B); in hppa_tr_init_disas_context()
4642 ctx->gva_offset_mask = cpu_env(cs)->gva_offset_mask; in hppa_tr_init_disas_context()
4645 ctx->privilege = PRIV_USER; in hppa_tr_init_disas_context()
4646 ctx->mmu_idx = MMU_USER_IDX; in hppa_tr_init_disas_context()
4647 ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); in hppa_tr_init_disas_context()
4649 ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; in hppa_tr_init_disas_context()
4650 ctx->mmu_idx = (ctx->tb_flags & PSW_D in hppa_tr_init_disas_context()
4651 ? PRIV_P_TO_MMU_IDX(ctx->privilege, ctx->tb_flags & PSW_P) in hppa_tr_init_disas_context()
4652 : ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); in hppa_tr_init_disas_context()
4655 cs_base = ctx->base.tb->cs_base; in hppa_tr_init_disas_context()
4656 ctx->iaoq_first = ctx->base.pc_first + ctx->privilege; in hppa_tr_init_disas_context()
4659 ctx->iaq_b.space = cpu_iasq_b; in hppa_tr_init_disas_context()
4660 ctx->iaq_b.base = cpu_iaoq_b; in hppa_tr_init_disas_context()
4662 ctx->iaq_b.base = cpu_iaoq_b; in hppa_tr_init_disas_context()
4664 uint64_t iaoq_f_pgofs = ctx->iaoq_first & ~TARGET_PAGE_MASK; in hppa_tr_init_disas_context()
4666 ctx->iaq_b.disp = iaoq_b_pgofs - iaoq_f_pgofs; in hppa_tr_init_disas_context()
4669 ctx->zero = tcg_constant_i64(0); in hppa_tr_init_disas_context()
4672 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; in hppa_tr_init_disas_context()
4673 ctx->base.max_insns = MIN(ctx->base.max_insns, bound); in hppa_tr_init_disas_context()
4680 /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ in hppa_tr_tb_start()
4681 ctx->null_cond = cond_make_f(); in hppa_tr_tb_start()
4682 ctx->psw_n_nonzero = false; in hppa_tr_tb_start()
4683 if (ctx->tb_flags & PSW_N) { in hppa_tr_tb_start()
4684 ctx->null_cond.c = TCG_COND_ALWAYS; in hppa_tr_tb_start()
4685 ctx->psw_n_nonzero = true; in hppa_tr_tb_start()
4687 ctx->null_lab = NULL; in hppa_tr_tb_start()
4696 tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); in hppa_tr_insn_start()
4698 iaoq_f = ctx->iaoq_first + ctx->iaq_f.disp; in hppa_tr_insn_start()
4699 if (iaqe_variable(&ctx->iaq_b)) { in hppa_tr_insn_start()
4702 iaoq_b = ctx->iaoq_first + ctx->iaq_b.disp; in hppa_tr_insn_start()
4703 diff = iaoq_b - iaoq_f; in hppa_tr_insn_start()
4704 /* Direct branches can only produce a 24-bit displacement. */ in hppa_tr_insn_start()
4710 ctx->insn_start_updated = false; in hppa_tr_insn_start()
4721 if (ctx->base.pc_next < TARGET_PAGE_SIZE) { in hppa_tr_translate_insn()
4723 ret = ctx->base.is_jmp; in hppa_tr_translate_insn()
4730 uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); in hppa_tr_translate_insn()
4734 * This will be overwritten by a branch. in hppa_tr_translate_insn()
4736 ctx->iaq_n = NULL; in hppa_tr_translate_insn()
4737 memset(&ctx->iaq_j, 0, sizeof(ctx->iaq_j)); in hppa_tr_translate_insn()
4738 ctx->psw_b_next = false; in hppa_tr_translate_insn()
4740 if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { in hppa_tr_translate_insn()
4741 ctx->null_cond.c = TCG_COND_NEVER; in hppa_tr_translate_insn()
4744 ctx->insn = insn; in hppa_tr_translate_insn()
4748 ret = ctx->base.is_jmp; in hppa_tr_translate_insn()
4749 assert(ctx->null_lab == NULL); in hppa_tr_translate_insn()
4753 set_psw_xb(ctx, ctx->psw_b_next ? PSW_B : 0); in hppa_tr_translate_insn()
4758 ctx->base.pc_next += 4; in hppa_tr_translate_insn()
4762 /* Note this also detects a priority change. */ in hppa_tr_translate_insn()
4763 if (iaqe_variable(&ctx->iaq_b) in hppa_tr_translate_insn()
4764 || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { in hppa_tr_translate_insn()
4765 ctx->base.is_jmp = DISAS_IAQ_N_STALE; in hppa_tr_translate_insn()
4773 ctx->iaq_f.disp = ctx->iaq_b.disp; in hppa_tr_translate_insn()
4774 if (!ctx->iaq_n) { in hppa_tr_translate_insn()
4775 ctx->iaq_b.disp += 4; in hppa_tr_translate_insn()
4782 if (ctx->iaq_n->base) { in hppa_tr_translate_insn()
4783 copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaq_n); in hppa_tr_translate_insn()
4784 ctx->iaq_b.base = cpu_iaoq_b; in hppa_tr_translate_insn()
4785 ctx->iaq_b.disp = 0; in hppa_tr_translate_insn()
4787 ctx->iaq_b.disp = ctx->iaq_n->disp; in hppa_tr_translate_insn()
4789 if (ctx->iaq_n->space) { in hppa_tr_translate_insn()
4790 tcg_gen_mov_i64(cpu_iasq_b, ctx->iaq_n->space); in hppa_tr_translate_insn()
4791 ctx->iaq_b.space = cpu_iasq_b; in hppa_tr_translate_insn()
4798 DisasJumpType is_jmp = ctx->base.is_jmp; in hppa_tr_tb_stop()
4800 DisasIAQE *f = &ctx->iaq_b; in hppa_tr_tb_stop()
4801 DisasIAQE *b = ctx->iaq_n; in hppa_tr_tb_stop()
4808 f = &ctx->iaq_f; in hppa_tr_tb_stop()
4809 b = &ctx->iaq_b; in hppa_tr_tb_stop()
4813 && (ctx->null_cond.c == TCG_COND_NEVER in hppa_tr_tb_stop()
4814 || ctx->null_cond.c == TCG_COND_ALWAYS)) { in hppa_tr_tb_stop()
4815 nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); in hppa_tr_tb_stop()
4838 for (DisasDelayException *e = ctx->delay_excp_list; e ; e = e->next) { in hppa_tr_tb_stop()
4839 gen_set_label(e->lab); in hppa_tr_tb_stop()
4840 if (e->set_n >= 0) { in hppa_tr_tb_stop()
4841 tcg_gen_movi_i64(cpu_psw_n, e->set_n); in hppa_tr_tb_stop()
4843 if (e->set_iir) { in hppa_tr_tb_stop()
4844 tcg_gen_st_i64(tcg_constant_i64(e->insn), tcg_env, in hppa_tr_tb_stop()
4847 install_iaq_entries(ctx, &e->iaq_f, &e->iaq_b); in hppa_tr_tb_stop()
4848 gen_excp_1(e->excp); in hppa_tr_tb_stop()
4856 target_ulong pc = dcbase->pc_first; in hppa_tr_disas_log()
4863 fprintf(logfile, "IN:\n0x000000b0: light-weight-syscall\n"); in hppa_tr_disas_log()
4866 fprintf(logfile, "IN:\n0x000000e0: set-thread-pointer-syscall\n"); in hppa_tr_disas_log()