riscv: Introduce local_hart_init

When Sstc is available make sure that even if we enable timer
interrupts nothing will happen. This is necessary for cases where
the unit tests actually intend to use

riscv: Introduce local_hart_init

When Sstc is available make sure that even if we enable timer
interrupts nothing will happen. This is necessary for cases where
the unit tests actually intend to use the SBI TIME extension and
aren't thinking about Sstc at all, like the SBI TIME test in
riscv/sbi where we can now remove the initialization.

We introduce local_hart_init() rather than something like
local_timer_init() for this since other non-timer-related CSRs will
also need to be set at init time in the future and we can just lump
them all together.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: sbi: Add IPI extension support

Add IPI EID and FID constants and a helper function to perform the IPI
SBI ecall.

Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
Signed-off-by:

riscv: sbi: Add IPI extension support

Add IPI EID and FID constants and a helper function to perform the IPI
SBI ecall.

Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: Define and use PHYS_PAGE_MASK

C doesn't extend the sign bit for unsigned types since there isn't a
sign bit to extend. This means a promotion of a u32 to a u64 results
in the upper 32 bits of

riscv: Define and use PHYS_PAGE_MASK

C doesn't extend the sign bit for unsigned types since there isn't a
sign bit to extend. This means a promotion of a u32 to a u64 results
in the upper 32 bits of the u64 being zero. When the u64 is then used
as a mask on another u64 the upper 32 bits get cleared, and that's
definitely not the intention of 'phys_addr & PAGE_MASK', which should
only clear the lower bits for page alignment. Create PHYS_PAGE_MASK
to do the right thing.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: mmu: Sanity check input physical addresses

Ensure physical addresses aren't using bits they shouldn't be.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

riscv: Support up to 34-bit physical addresses on rv32, sort of

Change virt_to_phys() and phys_to_virt() to use phys_addr_t instead
of unsigned long. This allows 32-bit builds to use physical addres

riscv: Support up to 34-bit physical addresses on rv32, sort of

Change virt_to_phys() and phys_to_virt() to use phys_addr_t instead
of unsigned long. This allows 32-bit builds to use physical addresses
over 32 bits wide (the spec allows up to 34 bits). But, to keep
things simple, we don't expect physical addresses wider than 32 bits
in most the library code (and that's ensured by sprinkling around
some asserts). IOW, the support is really only for unit tests which
want to test with an additional high memory region.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: sbi: Add dbcn write test

Added a unit test for the RISC-V SBI debug console write() and
write_byte() functions. The output of the tests must be inspected
manually to verify that the correct b

riscv: sbi: Add dbcn write test

Added a unit test for the RISC-V SBI debug console write() and
write_byte() functions. The output of the tests must be inspected
manually to verify that the correct bytes are written. For write(),
the expected output is 'DBCN_WRITE_TEST_STRING'. For write_byte(),
the expected output is 'a'.

Signed-off-by: Cade Richard <cade.richard@berkeley.edu>
[Applied all my suggested changes from the v4 review.]
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: move REG_L/REG_W in a dedicated asm.h file

These assembly macros will be used as part of the SSE entry assembly
code, export them in asm.h header.

Signed-off-by: Clément Léger <cleger@rivosi

riscv: move REG_L/REG_W in a dedicated asm.h file

These assembly macros will be used as part of the SSE entry assembly
code, export them in asm.h header.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: sbi: Add test for timer extension

Add a test for the set_timer function of the time extension. The test
checks that:
- The time extension is available
- The installed timer interrupt handler

riscv: sbi: Add test for timer extension

Add a test for the set_timer function of the time extension. The test
checks that:
- The time extension is available
- The installed timer interrupt handler is called
- The timer interrupt is received within a reasonable time interval
- The timer interrupt pending bit is cleared after the set_timer SBI
call is made when a time in the future is passed

The timer interrupt delay can be set using the TIMER_DELAY environment
variable in microseconds. The default delay value is 200 milliseconds.
Since the interrupt can arrive a little later than the specified delay,
allow some margin of error. This margin of error can be specified via
the TIMER_MARGIN environment variable in microseconds. The default
margin of error is 200 milliseconds.

Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
[Modified masked timer test and made a few cleanups.]
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: Add some delay and timer routines

Add a delay method that would allow tests to wait for some specified
number of cycles. Also add a conversion helper method between
microseconds and cycles. T

riscv: Add some delay and timer routines

Add a delay method that would allow tests to wait for some specified
number of cycles. Also add a conversion helper method between
microseconds and cycles. This conversion is done by using the timebase
frequency, which is obtained during setup via the device tree.

Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: Add method to probe for SBI extensions

Add a `sbi_probe` helper method that can be used by SBI extension tests
to check if a given extension is available.

Suggested-by: Andrew Jones <andrew.

riscv: Add method to probe for SBI extensions

Add a `sbi_probe` helper method that can be used by SBI extension tests
to check if a given extension is available.

Suggested-by: Andrew Jones <andrew.jones@linux.dev>
Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: Update exception cause list

Update the list of exception and interrupt causes to follow the latest
RISC-V privileged ISA specification (version 20240411 section 18.6.1).

Reviewed-by: Andrew

riscv: Update exception cause list

Update the list of exception and interrupt causes to follow the latest
RISC-V privileged ISA specification (version 20240411 section 18.6.1).

Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: Extend exception handling support for interrupts

Add install_irq_handler() to enable tests to install interrupt handlers.
Also add local_irq_enable() and local_irq_disable() to respectively
e

riscv: Extend exception handling support for interrupts

Add install_irq_handler() to enable tests to install interrupt handlers.
Also add local_irq_enable() and local_irq_disable() to respectively
enable and disable IRQs via the sstatus.SIE bit.

Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: Enable EFI boot

Mimicking Arm's setup_efi() and duplicating some code from riscv's
setup(), add the EFI setup code needed to boot unit tests from EFI-
capable bootloaders. The selftest unit t

riscv: Enable EFI boot

Mimicking Arm's setup_efi() and duplicating some code from riscv's
setup(), add the EFI setup code needed to boot unit tests from EFI-
capable bootloaders. The selftest unit test can now be run with

qemu-system-riscv64 \
-nodefaults -nographic -serial mon:stdio \
-accel tcg -cpu max \
-machine virt,pflash0=pflash0 \
-blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \
-smp 16 \
-kernel riscv/selftest.efi \
-initrd test-env \
-append 'selftest.efi foo bar baz' \
-machine acpi=off

where test-env has the environment variables
$ cat test-env
FOO=foo
BAR=bar
BAZ=baz

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: Enable building for EFI

Mimicking arm64 support, add configure and makefile changes to build
for EFI. Since the linker script is replaced also replace the initial
cstart code (also done like

riscv: Enable building for EFI

Mimicking arm64 support, add configure and makefile changes to build
for EFI. Since the linker script is replaced also replace the initial
cstart code (also done like arm64). Finally, provide a stub for
setup_efi() in order to allow compiling to complete (even though
tests can't yet run).

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

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riscv: Add isa string parsing

We can probably get away with just assuming several important
and popular extensions (at least everything covered by G), but
we'll also want to use some extensions whic

riscv: Add isa string parsing

We can probably get away with just assuming several important
and popular extensions (at least everything covered by G), but
we'll also want to use some extensions which we should ensure
are present by parsing the isa string. Add a parser and already
apply it to Sstc.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Enable vmalloc

Implement the functions that vmalloc depends on and let it enable the
MMU through setup_vm(). We can now also run the sieve test, so we
add it as well.

Signed-off-by: Andrew J

riscv: Enable vmalloc

Implement the functions that vmalloc depends on and let it enable the
MMU through setup_vm(). We can now also run the sieve test, so we
add it as well.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Enable the MMU in secondaries

Set each secondary satp to the same as the primary's and enable the
MMU when starting. We also change the memalign() to alloc_pages()
to prepare for enabling vma

riscv: Enable the MMU in secondaries

Set each secondary satp to the same as the primary's and enable the
MMU when starting. We also change the memalign() to alloc_pages()
to prepare for enabling vmalloc_ops. We always want an address
for the stack where its virtual address is the same as its physical
address, but vmalloc_ops.memalign wouldn't provide that.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Add MMU support

Add minimal page table defines and functions in order to build page
tables and enable the MMU.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thu

riscv: Add MMU support

Add minimal page table defines and functions in order to build page
tables and enable the MMU.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Populate memregions and switch to page allocator

Get the memory regions from the DT rather than just assuming we have
enough. Getting memory regions and setting their flags is also a
first st

riscv: Populate memregions and switch to page allocator

Get the memory regions from the DT rather than just assuming we have
enough. Getting memory regions and setting their flags is also a
first step to enabling the MMU. Also switch to the page allocator,
which is a second step to enabling the MMU.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Add SMP support

Implement the same SMP API that Arm has but using an SBI HSM
call instead of PSCI. Unlike Arm, riscv needs to always set
cpu0_calls_idle, because the boot hart doesn't have to

riscv: Add SMP support

Implement the same SMP API that Arm has but using an SBI HSM
call instead of PSCI. Unlike Arm, riscv needs to always set
cpu0_calls_idle, because the boot hart doesn't have to be the
first hart described in the DT, which means cpu0 may well be
a secondary. As usual, add a couple tests to selftest.c to
make sure everything works.

(The secondary boot process is also improved over Arm's a bit
by keeping boot data percpu, dropping the need for a lock. We
could create percpu data for Arm too, but that's left as future
work.)

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Add backtrace support

Enable stack unwinding, even when going through an exception, by
implementing backtrace() and pushing a frame pointer on the stack
in exception_vectors.

Signed-off-by:

riscv: Add backtrace support

Enable stack unwinding, even when going through an exception, by
implementing backtrace() and pushing a frame pointer on the stack
in exception_vectors.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Add exception handling

Steal more code from Linux to implement exception handling, but with
the same kvm-unit-tests API that Arm has. Also introduce struct
thread_info like Arm has in order t

riscv: Add exception handling

Steal more code from Linux to implement exception handling, but with
the same kvm-unit-tests API that Arm has. Also introduce struct
thread_info like Arm has in order to hold the handler pointers.
Finally, as usual, extend the selftest to make sure it all works.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Add initial SBI support

Add an SBI call function and immediately apply it to properly
exiting the test (instead of hanging) by invoking SBI shutdown
from exit(). Also seed an SBI test file wi

riscv: Add initial SBI support

Add an SBI call function and immediately apply it to properly
exiting the test (instead of hanging) by invoking SBI shutdown
from exit(). Also seed an SBI test file with a simple SBI test
that checks mvendorid is correctly extracted.

Run with e.g.
qemu-system-riscv64 -nographic -M virt \
-kernel riscv/sbi.flat \
-cpu rv64,mvendorid=45 \
-initrd sbi-env

and be happy that ctrl-a c q is no longer necessary to return to
the shell prompt. sbi-env has MVENDORID=45 in it.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Add DT parsing

Start building setup() by copying code from Arm and adding
dependencies along the way like bitops and a few more barriers.
We now parse the DT for the UART base address to be s

riscv: Add DT parsing

Start building setup() by copying code from Arm and adding
dependencies along the way like bitops and a few more barriers.
We now parse the DT for the UART base address to be sure we
find what we expect with the early base. We also parse the
CPU nodes to get the hartids, even though we don't yet support
booting secondaries. Finally, add parsing of bootargs to get
the command line and parsing of the environ to set the environment
variables, and then extend the selftest to ensure it all works.

We don't do proper memory setup yet, only just enough to allocate
memory for the environment variables and any another small mallocs
that may be necessary.

Note, we've added a banner, which Arm doesn't have, because we
need to separate the test output from OpenSBI output.

Run with
qemu-system-riscv64 -nographic -M virt \
-kernel riscv/selftest.flat \
-append 'foo bar baz' \
-initrd test-env \
-smp 16

where test-env is a text file with the environment, i.e.
$ cat test-env
FOO=foo
BAR=bar
BAZ=baz

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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riscv: Initial port, hello world

Add the minimal amount of code possible in order to launch a first
test, which just prints "Hello, world" using the expected UART
address of the QEMU virt machine. A

riscv: Initial port, hello world

Add the minimal amount of code possible in order to launch a first
test, which just prints "Hello, world" using the expected UART
address of the QEMU virt machine. Add files, stubs, and some support,
such as barriers and MMIO read/write along the way in order to
satisfy the compiler. Basically everything is either copied from
the arm64 port of kvm-unit-tests, or at least inspired by it, and,
in that case, the RISC-V Linux kernel code was copied.

Run with
qemu-system-riscv64 -nographic -M virt -kernel riscv/selftest.flat

and then go to the monitor (ctrl-a c) and use 'q' to quit, since
the unit test will just hang after printing hello world and the
exit code.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Acked-by: Thomas Huth <thuth@redhat.com>

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