1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASMRISCV_CSR_H_ 3 #define _ASMRISCV_CSR_H_ 4 #include <linux/const.h> 5 6 #define CSR_SSTATUS 0x100 7 #define CSR_STVEC 0x105 8 #define CSR_SSCRATCH 0x140 9 #define CSR_SEPC 0x141 10 #define CSR_SCAUSE 0x142 11 #define CSR_STVAL 0x143 12 #define CSR_SATP 0x180 13 #define CSR_TIME 0xc01 14 15 #define SR_SIE _AC(0x00000002, UL) 16 17 /* Exception cause high bit - is an interrupt if set */ 18 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 19 20 /* Exception causes */ 21 #define EXC_INST_MISALIGNED 0 22 #define EXC_INST_ACCESS 1 23 #define EXC_INST_ILLEGAL 2 24 #define EXC_BREAKPOINT 3 25 #define EXC_LOAD_MISALIGNED 4 26 #define EXC_LOAD_ACCESS 5 27 #define EXC_STORE_MISALIGNED 6 28 #define EXC_STORE_ACCESS 7 29 #define EXC_SYSCALL 8 30 #define EXC_HYPERVISOR_SYSCALL 9 31 #define EXC_SUPERVISOR_SYSCALL 10 32 #define EXC_INST_PAGE_FAULT 12 33 #define EXC_LOAD_PAGE_FAULT 13 34 #define EXC_STORE_PAGE_FAULT 15 35 #define EXC_INST_GUEST_PAGE_FAULT 20 36 #define EXC_LOAD_GUEST_PAGE_FAULT 21 37 #define EXC_VIRTUAL_INST_FAULT 22 38 #define EXC_STORE_GUEST_PAGE_FAULT 23 39 40 /* Interrupt causes */ 41 #define IRQ_S_SOFT 1 42 #define IRQ_VS_SOFT 2 43 #define IRQ_S_TIMER 5 44 #define IRQ_VS_TIMER 6 45 #define IRQ_S_EXT 9 46 #define IRQ_VS_EXT 10 47 #define IRQ_S_GEXT 12 48 #define IRQ_PMU_OVF 13 49 50 #ifndef __ASSEMBLY__ 51 52 #define csr_swap(csr, val) \ 53 ({ \ 54 unsigned long __v = (unsigned long)(val); \ 55 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 56 : "=r" (__v) : "rK" (__v) \ 57 : "memory"); \ 58 __v; \ 59 }) 60 61 #define csr_read(csr) \ 62 ({ \ 63 register unsigned long __v; \ 64 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 65 : "=r" (__v) : \ 66 : "memory"); \ 67 __v; \ 68 }) 69 70 #define csr_write(csr, val) \ 71 ({ \ 72 unsigned long __v = (unsigned long)(val); \ 73 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 74 : : "rK" (__v) \ 75 : "memory"); \ 76 }) 77 78 #define csr_read_set(csr, val) \ 79 ({ \ 80 unsigned long __v = (unsigned long)(val); \ 81 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 82 : "=r" (__v) : "rK" (__v) \ 83 : "memory"); \ 84 __v; \ 85 }) 86 87 #define csr_set(csr, val) \ 88 ({ \ 89 unsigned long __v = (unsigned long)(val); \ 90 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 91 : : "rK" (__v) \ 92 : "memory"); \ 93 }) 94 95 #define csr_read_clear(csr, val) \ 96 ({ \ 97 unsigned long __v = (unsigned long)(val); \ 98 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 99 : "=r" (__v) : "rK" (__v) \ 100 : "memory"); \ 101 __v; \ 102 }) 103 104 #define csr_clear(csr, val) \ 105 ({ \ 106 unsigned long __v = (unsigned long)(val); \ 107 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 108 : : "rK" (__v) \ 109 : "memory"); \ 110 }) 111 112 #endif /* !__ASSEMBLY__ */ 113 #endif /* _ASMRISCV_CSR_H_ */ 114