1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _ASMRISCV_CSR_H_ 3 #define _ASMRISCV_CSR_H_ 4 #include <linux/const.h> 5 6 #define CSR_SSTATUS 0x100 7 #define CSR_STVEC 0x105 8 #define CSR_SSCRATCH 0x140 9 #define CSR_SEPC 0x141 10 #define CSR_SCAUSE 0x142 11 #define CSR_STVAL 0x143 12 #define CSR_SATP 0x180 13 14 #define SR_SIE _AC(0x00000002, UL) 15 16 /* Exception cause high bit - is an interrupt if set */ 17 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 18 19 /* Exception causes */ 20 #define EXC_INST_MISALIGNED 0 21 #define EXC_INST_ACCESS 1 22 #define EXC_INST_ILLEGAL 2 23 #define EXC_BREAKPOINT 3 24 #define EXC_LOAD_MISALIGNED 4 25 #define EXC_LOAD_ACCESS 5 26 #define EXC_STORE_MISALIGNED 6 27 #define EXC_STORE_ACCESS 7 28 #define EXC_SYSCALL 8 29 #define EXC_HYPERVISOR_SYSCALL 9 30 #define EXC_SUPERVISOR_SYSCALL 10 31 #define EXC_INST_PAGE_FAULT 12 32 #define EXC_LOAD_PAGE_FAULT 13 33 #define EXC_STORE_PAGE_FAULT 15 34 #define EXC_INST_GUEST_PAGE_FAULT 20 35 #define EXC_LOAD_GUEST_PAGE_FAULT 21 36 #define EXC_VIRTUAL_INST_FAULT 22 37 #define EXC_STORE_GUEST_PAGE_FAULT 23 38 39 /* Interrupt causes */ 40 #define IRQ_S_SOFT 1 41 #define IRQ_VS_SOFT 2 42 #define IRQ_S_TIMER 5 43 #define IRQ_VS_TIMER 6 44 #define IRQ_S_EXT 9 45 #define IRQ_VS_EXT 10 46 #define IRQ_S_GEXT 12 47 #define IRQ_PMU_OVF 13 48 49 #ifndef __ASSEMBLY__ 50 51 #define csr_swap(csr, val) \ 52 ({ \ 53 unsigned long __v = (unsigned long)(val); \ 54 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 55 : "=r" (__v) : "rK" (__v) \ 56 : "memory"); \ 57 __v; \ 58 }) 59 60 #define csr_read(csr) \ 61 ({ \ 62 register unsigned long __v; \ 63 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 64 : "=r" (__v) : \ 65 : "memory"); \ 66 __v; \ 67 }) 68 69 #define csr_write(csr, val) \ 70 ({ \ 71 unsigned long __v = (unsigned long)(val); \ 72 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 73 : : "rK" (__v) \ 74 : "memory"); \ 75 }) 76 77 #define csr_read_set(csr, val) \ 78 ({ \ 79 unsigned long __v = (unsigned long)(val); \ 80 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 81 : "=r" (__v) : "rK" (__v) \ 82 : "memory"); \ 83 __v; \ 84 }) 85 86 #define csr_set(csr, val) \ 87 ({ \ 88 unsigned long __v = (unsigned long)(val); \ 89 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 90 : : "rK" (__v) \ 91 : "memory"); \ 92 }) 93 94 #define csr_read_clear(csr, val) \ 95 ({ \ 96 unsigned long __v = (unsigned long)(val); \ 97 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 98 : "=r" (__v) : "rK" (__v) \ 99 : "memory"); \ 100 __v; \ 101 }) 102 103 #define csr_clear(csr, val) \ 104 ({ \ 105 unsigned long __v = (unsigned long)(val); \ 106 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 107 : : "rK" (__v) \ 108 : "memory"); \ 109 }) 110 111 #endif /* !__ASSEMBLY__ */ 112 #endif /* _ASMRISCV_CSR_H_ */ 113